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http://dx.doi.org/10.9728/dcs.2013.14.1.1

A Study of Efficient CPLD Low Power Algorithm  

Youn, Choong-Mo (서일대학교 정보전자과)
Kim, Jae-Jin (강동대학교 신재생에너지과)
Publication Information
Journal of Digital Contents Society / v.14, no.1, 2013 , pp. 1-5 More about this Journal
Abstract
In this paper a study of efficient CPLD low power algorithm is proposed. Proposed algorithm applicate graph partition method using DAG. Circuit representation DAG. Each nodes set up cost. The feasible cluster create according to components of CPLD. Created feasible cluster generate power consumption consider the number of OR-term, the number of input and the number of output. Implement a circuit as select FC having the minimum power consumption. Compared with experiment [9], and power consumption was decreased. The proposed algorithm is efficient. this paper, we proposed FPGA algorithm for consider the power consumption.
Keywords
power consumption; Low power; CPLD; DAG;
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Times Cited By KSCI : 1  (Citation Analysis)
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1 Choong-Mo Youn, Jae-Jin Kim "A Study of FPGA Algorithm for consider the Power Consumption", Journal of Digital Contents Society Vol. 13 No. 1pp. 37-41, Mar. 2012   과학기술학회마을   DOI   ScienceOn
2 S. Devadas, S. malik, "A Survey of Optimization Techniques Targeting Low Power VLSI Circuits", in Proc. 32nd DAC, pp.242-247, June 1995.
3 A. Chandrakasan, T. Sheng, and R. Brodersen, "Low Power CMOS Digital Design", Journal of Solid State Circuits, vol. 27, no. 4, pp. 473-484, April 1992.   DOI   ScienceOn
4 S. ErColani, M. Favalli, M. Damiani, P. Olivo, B. Ricco, "Testability measures in pseudorandom testing", IEEE Trans. Computer-Aided Design., vol. 11, pp.794-800, 1992, June   DOI   ScienceOn
5 J. Cong and Y. Ding, "Flow Map : An 'Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, Vol. 13, No. 1, January 1994, pp.1-11   DOI   ScienceOn
6 Jason Helge Anderson, Stephen Dean Brown, "Technology Mapping for Large Complex PLDs", Design Automation Conference, 1998, pp. 698-703
7 Jae-Jin Kim, Hi-Seok Kim, Chi-Ho Lin, "A New Technology Mapping for CPLD under the time constraint" ASP-DAC, pp.235-238, January 2001.
8 E. M. Sentovice, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj,. P. R. Stephan, R. K. Brayton, A. Sangiovanni-Vincentelli, "SIS : A system for sequential Circuit Synthesis", Technical Report UCM/ERL M92/41, Electronics Research Laboratory, Department of Electrical Engineering and Computer Science, University of California, berkeley, 1992
9 Kim. Jae Jin, Lee. Kwan Houng, "An Efficient CPLD Technology Mapping considering Area and the Time Constraint", Journal of The Korea Socirty of Computer and Information, Vol. 10, No. 3, pp. 11-18, 2005
10 Kim. Jae Jin, Lee. Kwan Houng, "CLB-Based CPLDLow Power Technology Mapping Algorithm for Trade-off", Journal of The Korea Socirty of Computer and Information, Vol. 10, No. 2, pp. 49-57, 2005