Journal of Digital Contents Society (디지털콘텐츠학회 논문지)

Digital Contents Society (한국디지털콘텐츠학회)
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A Study of Efficient CPLD Low Power Algorithm

효율적인 CPLD 저전력 알고리즘에 관한 연구

  • Received : 2012.12.10
  • Accepted : 2013.03.16
  • Published : 2013.03.31
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Abstract

In this paper a study of efficient CPLD low power algorithm is proposed. Proposed algorithm applicate graph partition method using DAG. Circuit representation DAG. Each nodes set up cost. The feasible cluster create according to components of CPLD. Created feasible cluster generate power consumption consider the number of OR-term, the number of input and the number of output. Implement a circuit as select FC having the minimum power consumption. Compared with experiment [9], and power consumption was decreased. The proposed algorithm is efficient. this paper, we proposed FPGA algorithm for consider the power consumption.

본 논문은 효율적인 CPLD 저전력 알고리즘을 제안하였다. 제안한 알고리즘은 DAG를 이용한 그래프 분할 방식을 적용하였다. 주어진 회로를 DAG로 표현한 후 각각의 노드의 값을 설정하여 회로를 구현하고자 하는 CPLD의 구성 요소에 맞도록 매핑 가능 클러스터를 생성한다. 생성된 매핑 가능 클러스터의 OR 텀수와 입력 변수의, 출력 변수의 수를 고려하여 매핑 가능 클러스터의 소모 전력 값을 구한다. 생성된 매핑 가능 클러스터와 소모 전력 값을 고려하여 소모전력이 최소가 되는 매핑 가능 클러스터를 선정하여 회로를 구현한다. 실험은 [9]와 비교하였으며, 소모전력이 감소되어 알고리즘의 효율성이 입증되었다. 논문에서는 소모 전력을 위한 FPGA 알고리즘을 제안하였다.

Keywords

References

  1. S. Devadas, S. malik, "A Survey of Optimization Techniques Targeting Low Power VLSI Circuits", in Proc. 32nd DAC, pp.242-247, June 1995.
  2. A. Chandrakasan, T. Sheng, and R. Brodersen, "Low Power CMOS Digital Design", Journal of Solid State Circuits, vol. 27, no. 4, pp. 473-484, April 1992. https://doi.org/10.1109/4.126534
  3. S. ErColani, M. Favalli, M. Damiani, P. Olivo, B. Ricco, "Testability measures in pseudorandom testing", IEEE Trans. Computer-Aided Design., vol. 11, pp.794-800, 1992, June https://doi.org/10.1109/43.137524
  4. J. Cong and Y. Ding, "Flow Map : An 'Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs", IEEE Transactions on Computer-Aided Design of Integrated Circuit and Systems, Vol. 13, No. 1, January 1994, pp.1-11 https://doi.org/10.1109/43.273754
  5. Jason Helge Anderson, Stephen Dean Brown, "Technology Mapping for Large Complex PLDs", Design Automation Conference, 1998, pp. 698-703
  6. Jae-Jin Kim, Hi-Seok Kim, Chi-Ho Lin, "A New Technology Mapping for CPLD under the time constraint" ASP-DAC, pp.235-238, January 2001.
  7. E. M. Sentovice, K. J. Singh, L. Lavagno, C. Moon, R. Murgai, A. Saldanha, H. Savoj,. P. R. Stephan, R. K. Brayton, A. Sangiovanni-Vincentelli, "SIS : A system for sequential Circuit Synthesis", Technical Report UCM/ERL M92/41, Electronics Research Laboratory, Department of Electrical Engineering and Computer Science, University of California, berkeley, 1992
  8. Kim. Jae Jin, Lee. Kwan Houng, "An Efficient CPLD Technology Mapping considering Area and the Time Constraint", Journal of The Korea Socirty of Computer and Information, Vol. 10, No. 3, pp. 11-18, 2005
  9. Kim. Jae Jin, Lee. Kwan Houng, "CLB-Based CPLDLow Power Technology Mapping Algorithm for Trade-off", Journal of The Korea Socirty of Computer and Information, Vol. 10, No. 2, pp. 49-57, 2005
  10. Choong-Mo Youn, Jae-Jin Kim "A Study of FPGA Algorithm for consider the Power Consumption", Journal of Digital Contents Society Vol. 13 No. 1pp. 37-41, Mar. 2012 https://doi.org/10.9728/dcs.2012.13.1.037

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