• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.276-279
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• 2015

This paper presents two 3-stage D-band stacked amplifiers developed in a $0.13-{\mu}m$ SiGe BiCMOS technology, employed to compare the conventional cascode topology and the common-base (CB)/CB stacked topology. AMP1 employs two cascode stages followed by a CB/CB stacked stage, while AMP2 is composed of three CB/CB stacked stages. AMP1 showed a 17.1 dB peak gain at 143.8 GHz and a saturation output power of -4.2 dBm, while AMP2 showed a 20.4 dB peak gain at 150.6 GHz and a saturation output power of -1.3 dBm. The respective power dissipation was 42.9 mW and 59.4 mW for the two amplifiers. The results show that CB/CB stacked topology is favored over cascode topology in terms of gain near 140 GHz.

• Proceedings of the KIPE Conference
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• 2015.07a
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• pp.149-150
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• 2015

압전 마이크로머신 초음파 트랜스듀서(Piezoelectric micro-machined ultrasonic transducers)는 DC 바이어스 전압을 인가해야 구동되는 특성을 가지고 있다. 따라서 초음파 트랜스 듀서를 구동하기 위한 전력증폭기는 DC 바이어스 전압이 요구되므로 기존의 전력증폭기에 비해 효율이 매우 낮아지게 된다. 이를 해결하기 위해 본 논문에서는 압전 마이크로머신 초음파 트랜스듀서를 구동하기 위한 고효율 전력증폭기를 제안한다. 전력증폭기는 AMP부와 전원부로 나뉘며, AMP부는 Class B Amp를 사용하여 높은 증폭 선형성을 갖는다. 전원부는 Amp를 구동하기위한 DC-DC converter가 에너지 회수 동작을 하므로 전력증폭기의 효율을 높일 수 있다. 본 연구에서는 압전 마이크로머신 초음파 트랜스듀서를 구동하기 위한 전력증폭기 회로를 제시하고 시뮬레이션과 실험을 통해 동작 특성을 검증한다.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1521-1524
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• 1987

The performance of SCF can be improved with the Op-AMP which has the properties of high speed, large slew rate, and lower power dissipation. The OP-AMP used for SCF will be presented. For illustration, using this OP-AMP 5-th order LPF is designed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.768-776
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• 2014

Using a simplified high-frequency small-signal equivalent circuit model for BSIM3 MOSFET, the fully differential two-stage folded-cascode CMOS operational amplifier is analyzed to obtain its small-signal voltage transfer function. As a result, the expressions for dc gain, five zero frequencies, five pole frequencies, unity-gain frequency, and phase margin are derived for op amp design using design equations. Then the analysis result is verified through the comparison with Spice simulations of both a high speed op amp and a low power op amp designed for the $0.13{\mu}m$ CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2013.10a
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• pp.726-729
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• 2013

In this paper, low power and high slew rate CMOS rail to rail input/output opamp applicable for ouput buffer amp, in LCD source driver IC, is proposed. Proposed op-amp, is realized the characteristics of low power consumption and high slew rate adding the newly designed control stage of class-B to the conventional output stage of class-AB. From the simulation results, we know that the proposed opamp buffer can drive a 1000pF capacitive load with a 6.5V/us slew-rate, while drawing only the the power consumption of 1.19mW from 3.3V power supply.

• Journal of the Korean Society of Radiology
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• v.11 no.3
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• pp.101-108
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• 2017

DC/DC switching power converters are commonly used to generate a regulated DC output voltage with high efficiency. The advanced DC/DC converter uses a PWM-IC with OP-Amp. (Operational Amplifier) to control a MOSFET (metal-oxide semiconductor field effect transistor), which is a switching component, efficiently. In this paper, it is shown that the electrical characteristics of OP-Amp. are affected by radiations of ${\gamma}$ rays using $^{60}Co$ for TID (Total Ionizing Dose) testing and 5 heavy ions for SEL (Single Event Latch-up) testing. TID testing on OP-Amp. is accomplished up to the total dose of 30 krad, and the cross section($cm^2$) versus LET($MeV/mg/cm^2$) in the OP-Amp. operation is evaluated SEL testing after implementation of the controller board.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.5
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• pp.22-28
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• 1977

This is a design and analysis of the D.C. highly stabilized power source. This appratus has 10**-7 order of the voltage regulation and 40V, 1.5A, continuosly variable D.C. output. Authors inspected the effect of the OP Amp, FET and the load circuit to the stationary and transient characteristics of the apparatus. Authors found that it is a useful method for high performance of the stabilized power source to utilize IC OP Amp and FET as the elements of it.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.585-586
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• 2008

In this paper, a novel beta-multiplier reference current source circuit for the 800mV power-supply voltage is presented. In order to cope with the narrow input common-mode range of the OpAmp in the reference circuit, shunt resistive voltage divider branches were deployed. High gain OpAmp was designed to compensate intrinsic low output resistance of the MOS transistors. The proposed reference circuit was designed in a standard 0.18um CMOS process with nominal Vth of 420mV and -450mV for nMOS and pMOS transistor respectively. The total power consumption including OpAmp is less than 50uW.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.45 no.2
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• pp.26-36
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• 2008

Due to the differential and low voltage swing, Low Voltage Differential Signaling(LVDS) has been widely used for high speed data transmission with low power consumption. This paper proposes new LVDS I/O interface circuits for more than 1.3 Gb/s operation. The LVDS receiver proposed in this paper utilizes a sense amp for the pre-amp instead of a conventional differential pre-amp. The proposed LVDS allows more than 1.3 Gb/s transmission speed with significantly reduced driver output voltage. Also, in order to further improve the power consumption and noise performance, this paper introduces an inductance impedance matching technique which can eliminate the termination resistor. A new form of unfolded impedance matching method has been developed to accomplish the impedance matching for LVDS receivers with a sense amplifier as well as with a differential amplifier. The proposed LVDS I/O circuits have been extensively simulated using HSPICE based on 0.35um TSMC CMOS technology. The simulation results show improved power gain and transmission rate by ${\sim}12%$ and ${\sim}18%$, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.2
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• pp.118-123
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• 1989

In this paper, as we have integrated SCF for voice signal processing using CMOS circuit with the low power dissipation and the easy circuit design, it has been presented the simplified CMOS OP AMP design method with ${\pm}$5V pwoer source in order to use together with digital part. After an example about SCF CMOS OP AMP design, it has been performed layout appling channel width and length obtained by design method, and then its characteristics were simulated by SPICE 2G program. Therefoe, this design method will be applied the general CMOS OP AMP design in the electronic circuit.