• Title/Summary/Keyword: Polysilicon-oxide-nitride-oxide-silicon

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ONO Ruptures Caused by ONO Implantation in a SONOS Non-Volatile Memory Device

  • Kim, Sang-Yong;Kim, Il-Soo
    • Transactions on Electrical and Electronic Materials
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    • v.12 no.1
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    • pp.16-19
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    • 2011
  • The oxide-nitride-oxide (ONO) deposition process was added to the beginning of a 0.25 ${\mu}m$ embedded polysiliconoxide-nitride-oxide-silicon (SONOS) process before all of the logic well implantation processes in order to maintain the characteristics of basic CMOS(complementary metal-oxide semiconductor) logic technology. The system subsequently suffered severe ONO rupture failure. The damage was caused by the ONO implantation and was responsible for the ONO rupture failure in the embedded SONOS process. Furthermore, based on the experimental results as well as an implanted ion's energy loss model, processes primarily producing permanent displacement damages responsible for the ONO rupture failure were investigated for the embedded SONOS process.

A Study on the Abnormal Oxidation of Stacked Capacitor due to Underlayer Dependent Nitride Deposition (질화막 성장의 하지의존성에 따른 적층캐패시터의 이상산화에 관한 연구)

  • 정양희
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.1
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    • pp.33-40
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    • 1998
  • The composite SiO$_2$/Si$_3$N$_4$/SiO$_2$(ONO) film formed by oxidation on nitride film has been widely studied as DRAM stacked capacitor multi-dielectric films. Load lock(L/L) LPCVD system by HF cleaning is used to improve electrical capacitance and to scale down of effective thickness for memory device, but is brings a new problem. Nitride film deposited using HF cleaning shows selective deposition on poly silicon and oxide regions of capacitor. This problem is avoidable by carpeting chemical oxide using $H_2O$$_2$cleaning before nitride deposition. In this paper, we study the limit of nitride thickness for abnormal oxidation and the initial deposition time for nitride deposition dependent on underlayer materials. We proposed an advanced fabrication process for stacked capacitor in order to avoid selective deposition problem and show the usefulness of nitride deposition using L/L LPCVD system by $H_2O$$_2$cleaning. The natural oxide thickness on polysilicon monitor after HF and $H_2O$$_2$cleaning are measured 3~4$\AA$, respectively. Two substrate materials have the different initial nitride deposition times. The initial deposition time for polysilicon is nearly zero, but initial deposition time for oxide is about 60seconds. However the deposition rate is constant after initial deposition time. The limit of nitride thickness for abnormal oxidation under the HF and $H_2O$$_2$cleaning method are 60$\AA$, 48$\AA$, respectively. The results obtained in this study are useful for developing ultra thin nitride fabrication of ONO scaling and for avoiding abnormal oxidation in stacked capacitor application.

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A Study on SONOS Non-volatile Semiconductor Memory Devices for a Low Voltage Flash Memory (저전압 플래시메모리를 위한 SONOS 비휘발성 반도체기억소자에 관한 연구)

  • 김병철;탁한호
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.7 no.2
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    • pp.269-275
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    • 2003
  • Polysilicon-oxide-nitride-oxide-silicon(SONOS) transistors were fabricated by using 0.35${\mu}{\textrm}{m}$ complementary metal-oxide-semiconductor(CMOS) process technology to realize a low voltage programmable flash memory. The thickness of the tunnel oxide, the nitride, and the blocking oxide were 2.4nm, 4.0nm, and 2.5nm, respectively, and the cell area of the SONOS memory was 1.32$\mu$$m^2$. The SONOS device revealed a maximum memory window of 1.76V with a switching time of 50ms at 10V programming, as a result of the scaling effect of the nitride. In spite of scaling of nitride thickness, memory window of 0.5V was maintained at the end of 10 years, and the endurance level was at least 105 program/erase cycles. Over-erase, which was shown seriously in floating gate device, was not shown in SONOS device.

An Investigation of Locally Trapped Charge Distribution using the Charge Pumping Method in the Two-bit SONOS Cell

  • An, Ho-Myoung;Lee, Myung-Shik;Seo, Kwang-Yell;Kim, Byung-Cheul;Kim, Joo-Yeon
    • Transactions on Electrical and Electronic Materials
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    • v.5 no.4
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    • pp.148-152
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    • 2004
  • The direct lateral profile and retention characteristics of locally trapped-charges in the nitride layer of the two-bit polysilicon-oxide-nitride-oxide-silicon (SONOS) memory are investigated by using the charge pumping method. After charges injection at the drain junction region, the lateral diffusion of trapped charges as a function of retention time is directly shown by the results of the local threshold voltage and the trapped-charges quantities.

Realization of Two-bit Operation by Bulk-biased Programming Technique in SONOS NOR Array with Common Source Lines

  • An, Ho-Myoung;Seo, Kwang-Yell;Kim, Joo-Yeon;Kim, Byung-Cheul
    • Transactions on Electrical and Electronic Materials
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    • v.7 no.4
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    • pp.180-183
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    • 2006
  • We report for the first time two-bit operational characteristics of a high-density NOR-type polysilicon-oxide-nitride-oxide-silicon (SONOS) array with common source line (CSL). An undesired disturbance, especially drain disturbance, in the NOR array with CSL comes from the two-bit-per-cell operation. To solve this problem, we propose an efficient bulk-biased programming technique. In this technique, a bulk bias is additionally applied to the substrate of memory cell for decreasing the electric field between nitride layer and drain region. The proposed programming technique shows free of drain disturbance characteristics. As a result, we have accomplished reliable two-bit SONOS array by employing the proposed programming technique.

Progress of High-k Dielectrics Applicable to SONOS-Type Nonvolatile Semiconductor Memories

  • Tang, Zhenjie;Liu, Zhiguo;Zhu, Xinhua
    • Transactions on Electrical and Electronic Materials
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    • v.11 no.4
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    • pp.155-165
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    • 2010
  • As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

A study on the Bird's Beak-reduced LOCOS isolation by adding polysilicon (폴리 실리콘을 첨가하여 LOCOS 구조를 개량한 경우 소자분리 특성에 관한 연구)

  • Kim, Byeong-Yeol;Ryu, Hyeon-Gi;Park, Moon-Jin;Choi, Soo-Han;Song, Sung-Hae
    • Proceedings of the KIEE Conference
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    • 1987.07a
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    • pp.416-419
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    • 1987
  • The miniaturization of Bird's Beak generated at the field oxidation has been studied by adding polysilicon layer between the silicon nitride and pad oxide stack, which is the basic structure of Conventional LOCOS. The size and shape of Bird's Beak were intensively observed by SEM, and also the electrical characteristics of Bird's Beak-reduced LOCOS structure were compared with those of Conventional LOCOS. The length of Bird's Beak was reached up to $0.20-0.28{\mu}m$, while about to $0.50-0.53{\mu}m$ in conventional LOCOS, resulting in 60% reduction.

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