• Proceedings of the Materials Research Society of Korea Conference
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• 2012.05a
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• pp.67.1-67.1
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• 2012

Graphene has attracted much attention for future nanoelectronics due to its superior electrical properties. Owing to its extremely high carrier mobility and controllable carrier density, graphene is a promising material for practical applications, particularly as a channel layer of high-speed FET. Furthermore, the planar form of graphene is compatible with the conventional top-down CMOS fabrication processes and large-scale synthesis by chemical vapor deposition (CVD) process is also feasible. Despite these promising characteristics of graphene, much work must still be done in order to successfully develop graphene FET. One of the key issues is the process technique for gate dielectric formation because the channel mobility of graphene FET is drastically affected by the gate dielectric interface quality. Formation of high quality gate dielectric on graphene is still a challenging. Dirac voltage, the charge neutral point of the device, also strongly depends on gate dielectrics. Another performance killer in graphene FET is source/drain contact resistance, as the contact resistant between metal and graphene S/D is usually one order of magnitude higher than that between metal and silicon S/D. In this presentation, the key issues on graphene-based FET, including organic-inorganic hybrid gate dielectric formation, controlling of Dirac voltage, reduction of source/drain contact resistance, device structure optimization, graphene gate electrode for improvement of gate dielectric reliability, and CVD graphene transfer process issues are addressed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.3
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.4
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• pp.1-6
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• 2012

This paper presents the extraction and analysis of small-signal parameters of tunneling field-effect transistors (TFETs) by using TCAD device simulation. The channel lengths ($L_G$) of the simulated devices varies from 50 nm to 100 nm. The parameter extraction for TFETs have been performed by quasi-static small-signal model of conventional MOSFETs. The small-signal parameters of TFETs with different channel lengths were extracted according to gate bias voltage. The $L_G$-dependency of the effective gate resistance, transconductance, source-drain conductance, and gate capacitance are different with those of conventional MOSFET. The $f_T$ of TFETs is inverely proportional not to $L_G{^2}$ but to $L_G$.

• Journal of Sensor Science and Technology
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• v.14 no.3
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• pp.137-143
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• 2005

Research in the field of biosensor has enormously increased over the recent years. The metal-oxide semiconductor field effect transistor (MOSFET) type protein sensor offers a lot of potential advantages such as small size and weight, the possibility of automatic packaging at wafer level, on-chip integration of biosensor arrays, and the label-free molecular detection. We fabricated MOSFET protein sensor and proposed the gold-black electrode as the gate metal to improve the response. The experimental results showed that the output voltage of MOSFET protein sensor was varied by concentration of albumin proteins and the gold-black gate increased the response up to maximum 13 % because it has the larger surface area than that of planar-gold gate. It means that the expanded gate allows a larger number of ligands on same area, and makes the more albumin proteins adsorbed on gate receptor.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.35 no.6
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• pp.576-580
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• 2022

Semiconductor devices have evolved from 2D planar FETs to 3D bulk FinFETs, with aggressive device scaling. Bulk FinFETs make it possible to suppress short-channel effects. In addition, the use of low-k dielectric materials as a vacuum gate spacer have been suggested to improve the AC characteristics of the bulk FinFET. However, although the vacuum gate spacer is effective, correlation between the vacuum gate spacer and the short-channel-effects have not yet been compared or discussed. Using a 3D TCAD simulator, this paper demonstrates how to optimize bulk FinFETs including a vacuum gate spacer and to suppress short-channel effects.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.33 no.1
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• pp.16-20
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• 2020

In this study, a patterning method using self-aligned nanostructures was introduced to fabricate GaN-based fin-gate HEMTs with normally-off operation, as opposed to high-cost, low-productivity e-beam lithography. The honeycomb-shaped fin-gate channel width is approximately 40~50 nm, which is manufactured with a fine width using a proposed method to obtain sufficient fringing field effect. As a result, the threshold voltage of the fabricated device is 0.6 V, and the maximum normalized drain current and transconductance of Gm are 136.4 mA/mm and 99.4 mS/mm, respectively. The fabricated devices exhibit a smaller sub-threshold swing and higher Gm peak compared to conventional planar devices, due to the fin structure of the honeycomb channel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.113-119
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• 2005

4H-SiC planar MESFETs were fabricated using ion-implantation on semi-insulating substrate without recess gate etching. A modified RCA method was used to clean the substrate before each procedure. A thin, thermal oxide layer was grown to passivate the surface and then a thick field oxide was deposited by CVD. The fabricated MESFET showed good contact properties and DC/RF performances. The maximum oscillation frequency of 34 GHz and the cut-off frequency of 9.3 GHz were obtained. The power gain was 10.1 dB and the output power of 1.4 W was obtained for 1 mm-gate length device at 2 GHz. The fabricated MESFETs showed the charge trapping-free characteristics and were characterized by the extracted small-signal equivalent circuit parameters.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.8
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• pp.486-489
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• 2015

Power semiconductor device has a very long history among semiconductor, since the invention of low-pressure bipolar transistor 1947, and so far from small capacity to withstand voltage-current, high-speed and high-frequency characteristics have been developed with high function. In this study, the PWM IC Switch to the main parts used in IGBT (insulated gate bipolar transistor) for the low power loss and high drive capability of the simulator to Synopsys' T-CAD used by the 1,700 V NPT Planar IGBT, 1,700 V FS was a study of the Planar IGBT, the results confirmed that IGBT 1,700 V FS Planar is making about 11 percent less than the first designed NPT Planar IGBT.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.12
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• pp.1069-1074
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• 2005

In this work, nano-needle structures ate formed to solve problem, related to low density of quantum dots for nano floating gate memory. Such structures ate fabricated and electrical properties' of MIS devices fabricated on the nano-structures are studied. Nano floating gate memory based on quantum dot technologies Is a promising candidate for future non-volatile memory devices. Nano-structure is fabricated by reactive ion etching using $SF_6$ and $O_2$ gases in parallel RF plasma reactor. Surface morphology was investigated after etching using scanning electron microscopy Uniform and packed deep nano-needle structure is established under optimized condition. Photoluminescence and capacitance-voltage characteristics were measured in $Al/SiO_2/Si$ with nano-needle structure of silicon. we have demonstrated that the nano-needle structure can be applicable to non-volatile memory device with increased charge storage capacity over planar structures.

• Journal of the Korea institute for structural maintenance and inspection
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• v.18 no.4
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• pp.1-9
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• 2014

With the development of quantum computer, the development of the quantum-inspired search method applying the features of quantum mechanics and its application to engineering problems have emerged as one of the most interesting research topics. This algorithm stores information by using quantum-bit superposed basically by zero and one and approaches optional values through the quantum-gate operation. In this process, it can easily keep the balance between the two features of exploration and exploitation, and continually accumulates evolutionary information. This makes it differentiated from the existing search methods and estimated as a new algorithm as well. Thus, this study is to suggest a new minimum weight design technique by applying quantum-inspired search method into structural optimization of planar truss. In its mathematical model for optimum design, cost function is minimum weight and constraint function consists of the displacement and stress. To trace the accumulative process and gathering process of evolutionary information, the examples of 10-bar planar truss and 17-bar planar truss are chosen as the numerical examples, and their results are analyzed. The result of the structural optimized design in the numerical examples shows it has better result in minimum weight design, compared to those of the other existing search methods. It is also observed that more accurate optional values can be acquired as the result by accumulating evolutionary information. Besides, terminal condition is easily caught by representing Quantum-bit in probability.