Study on the Silicon Nano-needle Structure for Nano floating Gate Memory Application
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Jung, Sung-Wook
(성균관대학교 정보통신공학부)
Yoo, Jin-Su (성균관대학교 정보통신공학부) Kim, Young-Kuk (성균관대학교 정보통신공학부) Kim, Kyung-Hae (성균관대학교 정보통신공학부) Yi, Jun-Sin (성균관대학교 정보통신공학부) |
1 | R. Bez and A. Pirovano, 'Non-volatile memory technologies: emerging concepts and new materials', Materials Science in Semiconductor Processing, Vol. 7, No. 4-6, p. 349, 2004 |
2 | W. D. Brwon and J. E. Brewer, 'Nonvolatile Semiconductor Memory Technology', IEEE Press, New York, p. 156, 1998 |
3 | G. Molas, Barbara De Salvo, Gerard Ghibaudo, D. Mariolle, A. Toffoli, N. Buffet, R. Puglisi, S. Lombardo, and S. Deleonibus, 'Single electron effects and structural effects in ultrascaled silicon nanocrystal floatinggate memories', IEEE Transactions on Nanotechnology, Vol. 3, No.1, p. 42, 2004 |
4 | H. A. R. Wegener, 'Endurance model for textured poly floating gate memories', Technical Digest of the 1984 IEEE IEDM, Paper 17.7, p. 480, 1984 |
5 | D. Hisamoto, W.-C. Lee, J. Kedzierski, H. Takeuchi, K. Asano, C. Kuo, E. Anderson, T.-J. King, J. Boker, and C. Hu. 'FinFET - A self-aligned double-gate MOSFET scalable to 20 nm', IEEE Transactions on Electron Devices, Vol. 47, No. 12, p. 2320, 2000 |
6 | J. Kretz, L. Dreeskomfeld, J. Hartwich, and W. Rosner, '20 nm electron beam lithography and reactive ion etching for the fabrication of double gate FinFET devices', Microelectronic Engineering, Vol. 67, No.1, p. 763, 2003 |
7 | Chang L. L., Choi Y. K., Ha D. W., et al., 'EXtremely scaled silicon nano-CMOS devices', Proceedings of the IEEE, Vol. 91, No. 11, p. 1860, 2003 |
8 | M. Sugawara, 'Plasma Etching', Oxford University Press, New York, p. 180, 1998 |
9 | H. Jansen, M. de Boer, J Burger, R. Legtenberg, and M. Elwenspoek, 'The black silicon method. II : The effect of mask material and loading on the reactive ion etching of deep silicon trenches', Microelectronic Engineering, Vol. 27, No. 1-4, p. 475, 1995 |
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