• ETRI Journal
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• v.34 no.4
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• pp.518-526
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• 2012

This paper proposes LC voltage-controlled oscillator (VCO) phase-locked loop (PLL) and ring-VCO PLL topologies with low-phase noise. Differential control loops are used for the PLL locking through a symmetrical transformer-resonator or bilaterally controlled varactor pair. A differential compensation mechanism suppresses out-band spurious tones. The prototypes of the proposed PLL are implemented in a CMOS 65-nm or 45-nm process. The measured results of the LC-VCO PLL show operation frequencies of 3.5 GHz to 5.6 GHz, a phase noise of -118 dBc/Hz at a 1 MHz offset, and a spur rejection of 66 dBc, while dissipating 3.2 mA at a 1 V supply. The ring-VCO PLL shows a phase noise of -95 dBc/Hz at a 1 MHz offset, operation frequencies of 1.2 GHz to 2.04 GHz, and a spur rejection of 59 dBc, while dissipating 5.4 mA at a 1.1 V supply.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.6
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• pp.71-76
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• 2010

In this paper, a 120 GHz local oscillator(LO) for the sub-harmonic mixer in the THz transceiver with a carrier frequency of 240 GHz was designed and fabricated. A 120 GHz local oscillator was composed of 40 GHz PLL(Phase Locked Loop), 40 GHz BPF(Band Pass Filter), frequency tripler and 120 GHz BPF. The commercial model of the frequency tripler was used. The measured result of the 40 GHz PLL showed the phase noise of -105 dBc/Hz at the 100 kHz offset frequency. The measured result of 120 GHz BPF showed the insertion loss of 1.3 dB at center frequency of 119 GHz with bandwidth of 5 GHz. The output power of 120 GHz LO was measured to 6.6 dBm.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.313-321
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• 2014

A low-power low-cost polar transmitter for EDGE is designed in $0.18{\mu}m$ CMOS. A differential delta-sigma modulator (DSM) tunes a three-terminal voltage-controlled oscillator (VCO) to perform RF phase modulation, where the VCO tuning curve is digitally pre-compensated for high linearity and the carrier frequency is calibrated by a dual-mode low-power frequency-locked loop (FLL). A digital intermediate-frequency (IF) pulse-width5 modulator (PWM) drives a complementary power-switch followed by an LC filter to achieve envelope modulation with high efficiency. The proposed transmitter with 9mW power dissipation relaxes the time alignment between the phase and envelope modulations, and achieves an error vector magnitude (EVM) of 4% and phase noise of -123dBc/Hz at 400kHz offset frequency.

• Journal of information and communication convergence engineering
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• v.6 no.3
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• pp.275-278
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• 2008

In this paper, I propose the full CMOS FLL(frequency locked loop) circuit. The proposed FLL circuit has a simple structure which contains a FVC(frequency-to-voltage converter), an operational amplifier and a VCO(voltage controlled oscillator). The operation of FLL circuit is based on frequency comparison by the two FVC circuit blocks. The locking time of FLL is short compared to PLL(phase locked loop) circuit because the output signal of FLL is synchronized only in frequency. The circuit is designed by 0.35${\mu}m$ process and simulation carried out with HSPICE. Simulation results are shown to illustrate the performance of the proposed FLL circuit.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.62 no.12
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• pp.1700-1705
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• 2013

A second harmonic millimeter wave oscillator utilizing sub-harmonic injection-synchronization is presented. A 8.7GHz oscillator with MES-FET is designed, and is driven as a harmonic output oscillator at 17.4GHz by means of sub-harmonic injection-synchronization. The oscillator operates as a multiplier as well as a oscillator in this scheme. Adopting this method, a high sable, high frequency millimeter wave source is obtainable even though self-oscillating frequency of an oscillator is relatively low. The range of injection-synchronization is about 26MHz, and is proportional to the input sub-harmonic power. The spectrum analysis of the 2nd harmonic output frequency shows remarkably decreased the phase noise level.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.773-782
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• 2018

A frequency-locked loop(FLL) is a negative-feedback system that uses a frequency detector to improve the phase noise of a voltage-controlled oscillator(VCO). In this work, a theoretical analysis of the phase noise of a VCO in an FLL is presented. The analysis shows that the phase noise of the VCO follows the phase noise determined by the frequency detector and the loop filter within the FLL loop bandwidth, while the phase noise of the VCO appears outside the loop bandwidth. Therefore, it is possible to design an FLL that minimizes the phase noise of the VCO based on the theoretical analysis results. The theoretical phase noise results were verified through experiments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1982-1990
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• 1994

We implemented a PLDRO(Phase Locked Dielectric Resonator Oscillator) using the concept of the feedback property of PLL(Phase Locked Loop) for Ku-band(10.95-11.70 GHz). The conventional approaches to a PLDRO design use varactor diode tuning method.. But in theis paper, the PLDRO has the advantage of the frequency sensitivity to changes in the supple voltage of the oscillating device without the frequency-variable part by varactor diode voltage-control. and uses a SPD(Sampling Phase Detector) for phase-comparision. The PLDRO is composed of the DRO phase-locked to the reference signal of UHF band by using a SPD for high frequency stability and can be available for European FSS(Fixed Satellite Service) at 10.00GHz. The PLDRO generates the output power of 8.67 dBm at 10.00 GHz and has a phase noise of -81 dBc/Hz at 10 kHz offset from carrier. The hamonic and spurious characteristics have -42.33 dBc and -65dBc respectively. This PLDRO has much better frequency stability, lower phase noise, and more economical effect for a satellite system than conventional DRO.

• Journal of IKEEE
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• v.26 no.4
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• pp.714-721
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• 2022

A phase-locked loop (PLL)-based frequency synthesizer is proposed for a system on a chip (SoC) using multi-frequency clock signals. The proposed PLL-based frequency synthesizer consists of a charge pump PLL which is implemented by a phase frequency detector (PFD), a charge pump (CP), a loop filter, a voltage controlled oscillator (VCO), and a frequency divider, and an edge combiner. The PLL outputs a 12-phase clock by a VCO using six differential delay cells. The edge combiner synthesizes the frequency of the output clock through edge combining and frequency division of the 12-phase output clock of the PLL. The proposed PLL-based frequency synthesizer is designed using a 55-nm CMOS process with a 1.2-V supply voltage. It outputs three clocks with frequencies of 166 MHz, 83 MHz and 124.5MHz for a reference clock with a frequency of 20.75 MHz.

• Proceedings of the KIEE Conference
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• 2006.10c
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• pp.479-481
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• 2006

This paper describes a 2.5V, 320MHz low-noise and low-power Phase Locked Loop(PLL) using a noise-rejected Voltage Controlled ring Oscillator(VCO) fabricated in a TSMC 0.25um CMOS technology. In order to improve the power consumption and oscillation frequency of the PLL, The VCO consist of three-stage fully differential delay cells that can obtain the characteristic of high speed, low power and low phase noise. The VCO operates at 7MHz -670MHz. The oscillator consumes l.58mA from a 320MHz frequency and 2.5V supply. When the PLL with fully-differential ring VCO is locked 320MHz, the jitter and phase noise measured 26ps (rms), 157ps (p-p) and -97.09dB at 100kHz offset. We introduce and analysis the conditions in which ring VCO can oscillate for low-power operation.