• Transactions of the Korean Society of Machine Tool Engineers
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• v.16 no.6
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• pp.201-204
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• 2007

In this paper, fully embedded and miniaturized diplexer device has been developed and characterized for dual-band/mode CDMA handset applications. The size of the embedded diplexer is significantly reduced by embedding high Q circular spiral inductors and high DK MIM capacitors into a low cost organic package substrate. The fabricated diplexer has insertion losses and isolations of -0.5 and -23 dB at 824-894 MHz and -0.7 and -22 dB at 1850-1990 MHz, respectively. Its size is $3.9mm{\times}3.9mm{\times}0.77mm$. The fabricated diplexer is the smallest one which is fully embedded into a low cost organic package substrate.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.10
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• pp.889-895
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• 2002

Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.3
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• pp.63-69
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• 2013

The warpage of a bottom package of Package on Package(PoP) where a chip was mounted to a substrate by flip chip process was compared to that of a bottom package for which a chip was bonded to a substrate using die attach film(DAF). At the solder reflow temperature of $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpages of $57{\mu}m$ and $-102{\mu}m$, respectively. At the temperature range between room temperature and $260^{\circ}C$, the packages processed with flip chip bonding and DAF bonding exhibited warpage values ranging from $-27{\mu}m$ to $60{\mu}m$ and from $-50{\mu}m$ to $-15{\mu}m$, respectively.

• ETRI Journal
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• v.39 no.6
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• pp.866-873
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• 2017

We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.138-141
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• 2002

There are continuous efforts in the electronics industry to a reduced electronic package size. Reducing the size of electronic packages can be achieved by a variety of means, and for ball grid array(BGA) packages an effective method is to decrease the pitch between the individual balls. Chip scale package(CSP) and BGA are now one of the major package types. However, a reduced package size has the negative effect of reducing board-level reliability. The reliability concern is for the different thermal expansion rates of the two-substrate materials and how that coefficient CTE mismatch creates added stress to the BGA solder joint when thermal cycled. The point of thermal fatigue in a solder joint is an important factor of BGA packages and knowing at how many thermal cycles can be ran before failure in the solder BGA joint is a must for designing a reliable BGA package. Reliability of the package was one of main issues and underfill was required to improve board-level reliability. By filling between die and substrate, the underfill could enhance the reliability of the device. The effect of underfill on various thermomechanical reliability issues in $\mu$BGA packages is studied in this paper.

• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.35-41
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• 2016

Ceramic-metal based high power LED array package was developed via thick film LTCC technology using a glass-ceramic insulation layer and a silver conductor patterns directly printed on the aluminum heat sink substrate. The thermal resistance measurement using thermal transient tester revealed that ceramic-metal base LED package exhibited a superior heat dissipation property to compare with the previously known packaging method such as FR-4 based MCPCB. A prototype LED package sub-module with 50 watts power rating was fabricated using a ceramic-metal base chip-on-a board technology with minimized camber deformation during heat treatment by using partially covered glass-ceramic insulation layer design onto the aluminum heat spread substrate. This modified circuit design resulted in a camber-free packaging substrate and an enhanced heat transfer property compared with conventional MCPCB package. In addition, the partially covered design provided a material cost reduction compared with the fully covered one.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.09a
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• pp.147-164
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• 2001

1. "MLS", state of the art MCM-D wiring substrate. 2. High pin-count LSl assembly. 3. Higher speed needs higher packaging density. 4. Wiring substrate, the key of LSl packaging device. 5. "Inter-Layer Transferability", a new index for the performance of wiring substrates. 6. "MLTF package", a core-less flexible package for high pin-count LSl.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.11 s.353
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• pp.8-13
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• 2006

Recent RF SAW filters are made using a HTCC package with a CSP(chip scale Package) technology. This paper describes a development of a new $1.4{\times}1.1\;and\;2.0{\times}1.4mm$ RF SAW liters made by PCB substrate instead of HTCC package, and this technology can reduce the cost of materials down to 40%. We have investigated the multi-layered PCB substrate structures and raw materials to find out the optimal flip-bonding condition between the $LiTaO_3$ wafer and PCB substrates. Also the optimal materials and processing conditions of epoxy laminating film were found out through the experiments which can reduce the bending moment caused by the difference of the thermal expansion between the PCB substrate and laminating film. The new PCB SAW filter shows good electrical and reliability performances with respect to the present SAW filters.

• Journal of the Microelectronics and Packaging Society
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• v.26 no.4
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• pp.39-46
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• 2019

A stiffness-gradient soft PDMS/hard PDMS/FPCB stretchable package of the island-bridge structure was processed using the polydimethylsiloxane (PDMS) as the base substrate and the more stiff flexible printed circuit board (FPCB) as the island substrate, and its effective elastic modulus and stretchable deformation characteristics were analyzed. With the elastic moduli of the soft PDMS, hard PDMS, and FPCB to be 0.28 MPa, 1.74 MPa, and 1.85 GPa, respectively, the effective elastic modulus of the soft PDMS/hard PDMS/FPCB package was analyzed as 0.58 MPa. When the soft PDMS of the soft PDMS/hard PDMS/FPCB package was stretched to a tensile strain of 0.3, the strains occurring at hard PDMS and FPCB were found to be 0.1 and 0.003, respectively.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.2
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• pp.65-70
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• 2014

Warpage of top packages to form thin package-on-packages was measured with progress of their process steps such as PCB substrate itself, chip bonding, and epoxy molding. The $100{\mu}m$-thick PCB substrate exhibited a warpage of $136{\sim}214{\mu}m$. The specimen formed by mounting a $40{\mu}m$-thick Si chip to such a PCB using a die attach film exhibited the warpage of $89{\sim}194{\mu}m$, which was similar to that of the PCB itself. On the other hand, the specimen fabricated by flip chip bonding of a $40{\mu}m$-thick chip to such a PCB possessed the warpage of $-199{\sim}691{\mu}m$, which was significantly different from the warpage of the PCB. After epoxy molding, the specimens processed by die attach bonding and flip chip bonding exhibited warpages of $-79{\sim}202{\mu}m$ and $-117{\sim}159{\mu}m$, respectively.