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http://dx.doi.org/10.6117/kmeps.2014.21.2.065

Warpage Characteristics Analysis for Top Packages of Thin Package-on-Packages with Progress of Their Process Steps  

Park, D.H. (Department of Materials Science and Engineering, Hongik University)
Jung, D.M. (Department of Materials Science and Engineering, Hongik University)
Oh, T.S. (Department of Materials Science and Engineering, Hongik University)
Publication Information
Journal of the Microelectronics and Packaging Society / v.21, no.2, 2014 , pp. 65-70 More about this Journal
Abstract
Warpage of top packages to form thin package-on-packages was measured with progress of their process steps such as PCB substrate itself, chip bonding, and epoxy molding. The $100{\mu}m$-thick PCB substrate exhibited a warpage of $136{\sim}214{\mu}m$. The specimen formed by mounting a $40{\mu}m$-thick Si chip to such a PCB using a die attach film exhibited the warpage of $89{\sim}194{\mu}m$, which was similar to that of the PCB itself. On the other hand, the specimen fabricated by flip chip bonding of a $40{\mu}m$-thick chip to such a PCB possessed the warpage of $-199{\sim}691{\mu}m$, which was significantly different from the warpage of the PCB. After epoxy molding, the specimens processed by die attach bonding and flip chip bonding exhibited warpages of $-79{\sim}202{\mu}m$ and $-117{\sim}159{\mu}m$, respectively.
Keywords
Package-on-package; PoP; warpage; flip chip; die attach film; epoxy molding;
Citations & Related Records
Times Cited By KSCI : 3  (Citation Analysis)
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1 Y. Sawada, K. Harada and H. Fujioka, "Study of Package Warp Behavior for High-Performance Flip-Chip BGA", Microelectronics Reliability, 43(3), 465 (2003).   DOI   ScienceOn
2 J. Kim, S. Lee, J. Lee, S. Jung and C. Ryu, "Warpage Issues and Assembly Challenges Using Coreless Package", IPC APEX EXPO, (2012).
3 N. Boyard, A. Millischer, V. Sobotka, J. Bailleul and D. Delaunay, "Behaviour of a Moulded Composite Part: Modelling of Dilatometric Curve (Constant Pressure) or Pressure (Constant Volume) with Temperature and Conversion Degree Gradients", Composites Science and Technology 67(6), 943 (2007).   DOI   ScienceOn
4 M. J. Yim, R. Strode, R. Adimula and C. Yoo, "Effects of Material Properties on PoP Top Package Warpage Behaviors", Proc. 60th Electronic Components and Technology Conference (ECTC), Las Vegas, 1071, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2010).
5 K. Ishibashi, "PoP (Package-on-Package) Stacking Yield Loss Study", Proc. 57th Electronic Components and Technology Conference (ECTC), Reno NV, 1403 (2007).
6 W. Y. Kong, J. K. Kim and M. F. Yuen, "Warpage in Plastic Packages: Effects of Process Conditions, Geometry and Materials", IEEE Transitions on Electronics Packaging Manufacturing, 26(3), 245 (2003).   DOI   ScienceOn
7 C. H. Chien, Y. C. Chen, Y. T. Chio, T. Chen, C. C. Hsieh, J. J. Yan, W. Z Chen and Y. D. Wua, "Influences of the Moisture Absorption on PBGA Package's Warpage during IR Reflow Process", Microelectronics Reliability, 43, 131 (2003).   DOI
8 C. G. Kim, H. S. Choi, M. S. Kim, and T. S. Kim, "Packaging Substrate Bending Prediction due to Residual Stress", J. Microelectron. Packag. Soc., 20(1), 21 (2013).   DOI   ScienceOn
9 H. Eslampour, Y. C. Kim, S. W. Park, T. and W. Lee, "Low Cost Cu Column fcPoP Technology", Proc. 62nd Electronic Components and Technology Conference (ECTC), San Diego, 871, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2012).
10 J. Zhao, Y. Luo, Z. Huang and R. Ma, "Effects of Package Design on Top PoP Package Warpage", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1081, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008).
11 H. Tang, J. Nguyen, J. Zhang and I. Chien, "Warpage Study of a Package on Package Configuration", International Symposium on High Density Packaging (HDP), Shanghai, 1 (2007).
12 B. H. Lee, M. K. Kim and J. W. Joo, "Thermo-Mechanical Behavior of WB-PBGA Packages with Pb-Sn Solder and Lead-Free Solder Using Moire Interferometry", J. Microelectron. Packag. Soc., 17(3), 17 (2010).
13 JEDEC Standard JESD22-B112A, "Package Warpage Measurement of Surface-Mount Integrated Circuits at Elevated Temperature", JEDEC Solid State Technology Association, Arlington (2009).
14 S. Michaelides and S. K. Sitaraman, "Die Cracking and Reliable Die Design for Flip-Chip Assemblies", IEEE Transactions on Advanced Packaging, 22(4), 602 (1999).   DOI
15 International Data Corporation, "Worldwide Smart Connected Device Tracker", International Data Corporation (IDC). Inc. Mar.(2013) from http:// www.idc.com
16 K. H. Kim, H. Lee, J. W. Jeong, J. H. Kim and S. H. Choa, "Numerical Analysis of Warpage and Stress for 4-layer Stacked FBGA Package", J. Microelectron. Packag. Soc., 19(2), 7 (2012).
17 N. Vijayaragavan, F. Carson and A. Mistry, "Package on Package Warpage - Impact on Surface Mount Yields and Board Level Reliability", Proc. 58th Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 389, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2008).
18 P. Sun, V. C. Leung, B. Xie, V. W. Ma and D. X. Shi, "Warpage Reduction of Package-on-Package (PoP) Module by Material Selection & Process Optimization", International Conference on Electronic Packaging Technology & High Density Packaging (ICEPT-HDP), Shanghai, 1 (2008).
19 Y. H. Cho, S. E. Kim and S. Kim, "Wafer Level Bonding Technology for 3D Stacked IC", J. Microelectron. Packag. Soc., 20(1), 7 (2013).   DOI   ScienceOn
20 T. Hao, J. Nguyen, J. Zhang and I. Chien, "Warpage Study of a Package on Package Configuration", IEEE Components, International Symposium on High Density Packaging and Microsystem Integration (HDP), Shanghai, 1 (2007).
21 S. Y. Yang, Y. Jeon, S. Lee and K. Paik, "Solder Reflow Process Induced Residual Warpage Measurement and Its Influence on Reliability of Flip-Chip Electronic Packages", Microelectronics and Reliability 46(2-4), 512 (2006).   DOI   ScienceOn
22 M. J. Yim, R. Strode, R. Adimula, J. J. Zhang and C. Yoo, "Ultra Thin Top Package using Compression Mold: Its Warpage Control", Proc. 61st Electronic Components and Technology Conference (ECTC), Lake Buena Vista, 1141, IEEE Components, Packaging and Manufacturing Technology Society (CPMT) (2011).
23 Gartner, "Forecast: PCs, Ultramobiles, and Mobile Phones, Worldwide, 2011-2018, 1Q14 Update", Gartner. Inc. Mar.(2014) from http://www.gartner.com/document/2685317