• 한국광학회지
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• 제24권6호
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• pp.342-346
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• 2013

고출력 LED 패키지의 방열 특성 향상을 위하여, 다이 접합부에 실리콘 접착제와 금속 패턴의 병렬 접합 구조를 적용하여 열 유동 해석을 수행하였다. 그 결과, LED 칩에서 발생한 열은 주로 금속 패턴 구조물을 통해 기판으로 효과적으로 전달되고 있으나, 패턴 구조물의 크기에 따라 효율의 차이가 있음을 확인하였고, 그 효과를 정량화하기 위해 정규화 길이를 도입하여 칩과 금속 패턴 구조물의 면적에 따른 열 저항을 비교하였다. 정규화 길이가 길어지면 금속 패턴 구조물에 의한 열 우회 경로가 칩에 고르게 분포하여 열 저항이 감소하였으며, 그 값은 단순 병렬 열 저항 이론 값보다 다소 큰 수치로 수렴하지만, 충분한 열 저항 개선 효과를 얻을 수 있었다.

• 전자공학회논문지A
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• 제32A권12호
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• pp.149-158
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• 1995

This paper describes the development of a software tool LCD FRAME that may guide the analyzing process for the electrical characteristics and the design procedure for constructing the thin film transistor liquid crystal display(TFT/LCD) packages. LCD FRAME can analyze its electrical characteristics from the TFT/LCD system package configuration, and provide the design variables to meet the user's requirements. These analysis and design procedure can be done in real time according to the model at simplified package level of TFT/LCD. LCD_FRAME is an object-oriented expert system which considers package elements as objects. With this LCD_FRAME software tool, we analyzed the I-V characteristics of a-Si TFT and its signal distortion which has maximum 1.58 $\mu$s delay along the panel scan line of the package containing 480 ${\times}$ 240 pixels. We designed the package structure of maximum 6.35 $\mu$s signal delays and 3360 ${\times}$ 780 pixels, and as a result we showed that the proper structure of 20 $\mu$m scan line width, 60$\mu$m panel TFT gate width and 8 $\mu$m gate length. This LCD_FRAME software tool provides results of the analysis and the design in the form of input files of the SPICE program, text data files, and graphic charts.

• E2M - 전기 전자와 첨단 소재
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• 제10권6호
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• pp.519-527
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• 1997

The micro crack was occurred where the stress concentrated by the thermal stress which was induced during the cooling period after molding process or by the various reliability tests. In order to estimate the possibility of development from inside micro crack to outside fracture, the fracture toughness of EMC should be measured under the various applicable condition. But study was conducted very rarely for the above area. In order to provide a was to decide the fracture resistance of EMC (Epoxy Molding Compound) of plastic package which is produced by using transfer molding method, measuring fracture is studied. The specimens were made with various EMC material. The diverse combination of test conditions, such as different temperature, temperature /humidity conditions, different filler shapes, and post cure treatment, were tried to examine the effects of environmental condition on the fracture toughness. This study proposed a way which could improve the reliability of LOC(Lead On Chip) type package by comparing the measured $J_{IC}$ of EMC and the calculated J-integral value from FEM(Finite Element Method). The measured $K_{IC}$ value of EMC above glass transition temperature dropped sharply as the temperature increased. The $K_{IC}$ was observed to be higher before the post cure treatment than after the post cure treatment. The change of $J_{IC}$ was significant by time change. J-integral was calculated to have maximum value the angle of the direction of fracture at the lead tip was 0 degree in SOJ package and -30 degree in TSOP package. The results FEM simulation were well agreed with the results of measurement within 5% tolerance. The package crack was proved to be affected more by the structure than by the composing material of package. The structure and the composing material are the variables to reduce the package crack.ack.

• 한국포장학회지
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• 제12권1호
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• pp.45-53
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• 2006

Thermal insulation is used in a variety of applications to protect temperature sensitive products from thermal damage. Several factors affect the performance of insulation packages. Among these factors, the thermal resistance of the insulating wall is the most important factor to determine the performance of the insulating package. In many cases, insulating wall consists of multi-layered structure and the heat transfer through this structure is a very complex process. In this study, an one-dimensional mathematical model, which includes all of the heat transfer principles covering conduction, convection and radiation in multi-layered structure, were developed. Based on this model, several heat transfer phenomena occurred in the air space between the layer of the insulating wall were investigated. From the simulation results, it was observed that the heat transfer through the air space between the layer were dominated by conduction and radiation and the low emissivity of the surface of each solid layer of the wall can dramatically increase the thermal resistance of the wall. For practical use, an equation was derived for the calculation of the thermal resistance of a multi-layered wall.

• 한국전기전자재료학회논문지
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• 제15권10호
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• pp.889-895
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• 2002

Wafer level packaging is gain mote momentum as a low cost, high performance solution for RF-MEMS devices. In this work, the flip-chip method was used for the wafer level packaging of RF-MEMS devices on the quartz substrate with low losses. For analyzing the EM (electromagnetic) characteristic of proposed packaging structure, we got the 3D structure simulation using FEM (finite element method). The electric field distribution of CPW and hole feed-through at 3 GHz were concentrated on the hole and the CPW. The reflection loss of the package was totally below 23 dB and the insertion loss that presents the signal transmission characteristic is above 0.06 dB. The 4-inch Pyrex glass was used as a package substrate and it was punched with air-blast with 250${\mu}{\textrm}{m}$ diameter holes. We made the vortical feed-throughs to reduce the electric path length and parasitic parameters. The vias were filled with plating gold. The package substrate was bonded with the silicon substrate with the B-stage epoxy. The loss of the overall package structure was tested with a network analyzer and was within 0.05 dB. This structure can be used for wafer level packaging of not only the RF-MEMS devices but also the MEMS devices.

• 조명전기설비학회논문지
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• 제30권3호
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• pp.30-38
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• 2016

In this research, a 6W white LED package with a Glass Remote Phosphor was developed to improve the life of an LED package. The Glass Remote Phosphor was fabricated by the Phosphor in Glass (PiG) method, wherein phosphor YAG:Ce was mixed with glass frit and then heat treated. A paste with 75wt.% of a phosphor substance and 25wt.% glass frit was coated on a glass substrate two times using the screen-printing technique and heat-treated at $800^{\circ}C$ ; this structure gave a luminous efficacy of 136.1lm/W, color rendering index of 74Ra, and color temperature of 5,342K, thus satisfying the requirements as a light source for lighting. Moreover, an IES LM-80 accelerated life test was conducted on the same LED package for 6,000h in order to estimate the L70 lifetime based on IES TM-21. The results showed guaranteed lifetimes of 213,000h at $55^{\circ}C$, 245,000h at $85^{\circ}C$, and 209,000h at $95^{\circ}C$.

• 대한전자공학회논문지SD
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• 제47권4호
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• pp.69-74
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• 2010

알루미늄 양극산화(aluminum anodization)의 선택적인 적용을 통하여 DRAM 소자를 위한 새로운 패키지 기판을 제작하였다. 에폭시 계열의 코어(core)와 구리의 적층 형태로 제작되는 일반적인 패키지 기판과는 달리 제안된 패키지 기판은 아래층 알루미늄(aluminum), 중간층 알루미나(alumina, $Al_2O_3$) 그리고 위층 구리(copper)로 구성된다. 알루미늄 기판에 양극산화 공정을 수행함으로써 두꺼운 알루미나를 얻을 수 있으며 이를 패키지 기판의 유전체로 사용할 수 있다. 알루미나층 위에 구리 패턴을 배치함으로써 새로운 2층 금속 구조의 패키지 기판을 완성하게 된다. 또한 알루미늄 양극산화를 선택적인 영역에만 적용하여 내부가 완전히 채워져 있는 비아(via) 구조를 구현할 수 있다. 패키지 설계 시에 비아 인 패드(via in pad) 구조를 적용하여 본딩 패드(bonding pad) 및 볼 패드(ball pad) 상에 비아를 배치하였다. 상기 비아 인 패드 배치 및 2층 금속 구조로 인해 패키지 기판의 배선 설계가 보다 수월해지고 설계 자유도가 향상된다. 새로운 패키지 기판의 주요 설계인자를 분석하고 최적화하기 위하여 테스트 패턴의 2차원 전자기장 시뮬레이션 및 S-파라미터 측정을 진행하였다. 이러한 설계인자를 바탕으로 모든 신호 배선은 우수한 신호 전송을 얻기 위해서 $50{\Omega}$의 특성 임피던스를 가지는 coplanar waveguide(CPW) 및 microstrip 기반의 전송선 구조로 설계되었다. 본 논문에서는 패키지 기판 구조, 설계 방식, 제작 공정 및 측정 등을 포함하여 양극산화 알루미늄 패키지 기판의 특성과 성능을 분석하였다.

• 대한기계학회:학술대회논문집
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• 대한기계학회 2003년도 추계학술대회
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• pp.1407-1412
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• 2003

In MEMS devices, packaging induced stress or stress induced structure deformation become increasing concerns since it directly affects the performance of the device. In this paper, deformation behavior of MEMS gyroscope package subjected to temparature change is investigated using high-sensitivity $Moir{\acute{e}}$ interferometry. Using the real-time $Moir{\acute{e}}$ setup, fringe patterns are recorded and analyzed at several temperatures. Temperature dependent analyses of warpages and extensions/contractions of the package are presented. Linear elastic behavior is documented in the temperature region of room temperature to $125^{\circ}C$. Analysis of the package reveals that global bending occurs due to the mismatch of thermal expansion coefficient between the chip, the molding compond and the PCB.

• 대한기계학회논문집
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• 제6권4호
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• pp.384-389
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• 1982

It is necessary that machine tool structures should be designed so that they will cause a minimum chance of machining chatter. In order to do this, a computer program package is developed utilizing Finite Element Method, modal flexibility and energy balance method. Validity of the program package is verified through computer simulation analysis and impulse test of a simplified machine tool structure.

• 마이크로전자및패키징학회지
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• 제20권3호
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• pp.31-35
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• 2013

TSOP(Thin Small Outline Package)는 가전제품, 자동차, 모바일, 데스크톱 PC등을 위한 저렴한 비용의 패키지로, 리드 프레임을 사용하는 IC패키지이다. TSOP는 BGA와 flip-chip CSP에 비해 우수한 성능은 아니지만, 저렴한 가격 때문에 많은 분야에 널리 사용되고 있습니다. 그러나, TSOP 패키지에서 몰딩공정 할 때 리드프레임의 열적 처짐 현상이 빈번하게 일어나고, 반도체 다이와 패드 사이의 Au 와이어 떨어짐 현상이 이슈가 되고 있다. 이러한 문제점을 해결하기 위해서는 리드프레임의 구조를 개선하고 낮은 CTE를 갖는 재료로 대체해야 한다. 본 연구에서는 열적 안정성을 갖도록 리드프레임 구조 개선을 위해 수치해석적 방법으로 진행하였다. TSOP 패키지에서 리드프레임의 열적 처짐은 반도체와 다이 사이의 거리(198 um~366 um)에서 안티-디플렉션의 위치에 따라 시뮬레이션을 진행하였다. 안티-디플렉션으로 TSOP 패키지의 열적 처짐은 확실히 개선되는 것을 확인 했다. 안티-디플렉션의 위치가 inside(198 um)일 때 30.738 um 처짐을 보였다. 이러한 결과는 리드프레임의 열적 팽창을 제한하는데 안티-디플렉션이 기여하고 있기 때문이다. 그러므로 리드프레임 패키지에 안티-디플렉션을 적용하게 되면 낮은 CTE를 갖는 재료로 대체하지 않아도 열적 처짐을 향상시킬 수 있음을 기대할 수 있다.