Browse > Article

DRAM Package Substrate Using Aluminum Anodization  

Kim, Moon-Jung (Division of Electrical Electronics and Control Engineering, Kongju National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.47, no.4, 2010 , pp. 69-74 More about this Journal
Abstract
A new package substrate for dynamic random access memory(DRAM) devices has been developed using selective aluminum anodization. Unlike the conventional substrate structure commonly made by laminating epoxy-based core and copper clad, this substrate consists of bottom aluminum, middle anodic aluminum oxide and top copper. Anodization process on the aluminum substrate provides thick aluminum oxide used as a dielectric layer in the package substrate. Placing copper traces on the anodic aluminum oxide layer, the resulting two-layer metal structure is completed in the package substrate. Selective anodization process makes it possible to construct a fully filled via structure. Also, putting vias directly in the bonding pads and the ball pads in the substrate design, via in pad structure is applied in this work. These arrangement of via in pad and two-layer metal structure make routing easier and thus provide more design flexibility. In a substrate design, all signal lines are routed based on the transmission line scheme of finite-width coplanar waveguide or microstrip with a characteristic impedance of about $50{\Omega}$ for better signal transmission. The property and performance of anodic alumina based package substrate such as layer structure, design method, fabrication process and measurement characteristics are investigated in detail.
Keywords
Aluminum anodization; package substrate; transmission line; via in pad;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
연도 인용수 순위
1 W. Koh, "Memory device packaging - from leadframe packages to wafer level packages," in Proc. High Density Microsystem Design and Packaging and Component Failure Analysis, pp. 21-24, 2004.
2 G. Ramakrishna et al., "Micro-scale plasticity effects in microvia reliability analysis," in Proc. Electron. Components Technol. Conf., pp. 1304-1309, 2002.
3 Samsung 1Gb DDR2 SDRAM datasheet, input/output capacitance, www.samsung.com.
4 C. T. Tsai, "Package inductance characterization at high frequencies," IEEE Trans. Components, Packaging and Manufacturing Technology, Part B, Vol. 17, no. 2, pp. 175-181, 1994.   DOI   ScienceOn
5 W. J. Bernard and S. M. Florio, "Anodic Oxide Growth on Aluminum in the Presence of a Thin Thermal Oxide Layer," J. Electrochem. Soc., Vol. 134, pp. 1205-1211, 1987.   DOI   ScienceOn
6 Y. Eo and W. R. Eisenstadti, "High-speed VLSI interconnect modeling based on S-parameter measurements," IEEE Trans. Components, Packaging and Manufacturing Technology, Vol. 16, no. 5, pp. 555-562, 1993.
7 C. K. Yew et al., "Board on chip-ball grid array (BOC-BGATM) package - A new design for high frequency application (package design and reliability)," in Proc. Electron. Components Technol. Conf., pp. 353-357, 1997.
8 S. H. Jeong and K. H. Lee, "Field emission properties of low-density carbon nanotubes prepared on anodic aluminum-oxide template," Journal of the Korean Physical Society, Vol. 45, no. 2, pp. 252-255, 2004.
9 H. Pan et al., "Electrical-bridge model on the self-organized growth of nanopores in anodized alumina oxide," IEEE Trans. Nanotechnol., Vol. 3, no. 4, pp. 462-467, 2004.   DOI   ScienceOn
10 J. Jeong et al., "Electrical characterization of ball grid array packages from S-parameter measurements below 500 MHz," IEEE Trans. Adv. Packag., Vol. 22, no. 3, pp. 343-347, 1999.   DOI   ScienceOn
11 J. Zhao, J. Zhang, and J. Fang, "Effects of power/ground via distribution on the power/ground performance of C4/BGA packages," in Proc. Electrical Performance of Electronic Packaging, pp. 177-180, 1998.
12 F. X. Che and J. E. Luan, "Effect of microstructure design on reliability of FBGA lead-free solder joints," in Proc. Microelectronics and Packaging Conference, pp. 1-6, 2009.