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http://dx.doi.org/10.6117/kmeps.2013.20.3.031

Numerical Analysis for Thermal-deformation Improvement in TSOP(Thin Small Outline Package) by Anti-deflection Adhesives  

Kim, Sang-Woo (Rare metal R&D Group, Korea institute of Industrial Technology)
Lee, Hai-Joong (Rare metal R&D Group, Korea institute of Industrial Technology)
Lee, Hyo-Soo (Rare metal R&D Group, Korea institute of Industrial Technology)
Publication Information
Journal of the Microelectronics and Packaging Society / v.20, no.3, 2013 , pp. 31-35 More about this Journal
Abstract
TSOP(Thin Small Outline Package) is the IC package using lead frame, which is the type of low cost package for white electronics, auto mobile, desktop PC, and so on. Its performance is not excellent compared to BGA or flip-chip CSP, but it has been used mostly because of low price of TSOP package. However, it has been issued in TSOP package that thermal deflection of lead frame occurs frequently during molding process and Au wire between semiconductor die and pad is debonded. It has been required to solve this problem through substituting materials with low CTE and improving structure of lead frame. We focused on developing the lead frame structure having thermal stability, which was carried out by numerical analysis in this study. Thermal deflection of lead frame in TSOP package was simulated with positions of anti-deflection adhesives, which was ranging 198 um~366 um from semiconductor die. It was definitely understood that thermal deflection of TSOP package with anti-deflection adhesives was improved as 30.738 um in the case of inside(198 um), which was compared to that of the conventional TSOP package. This result is caused by that the anti-deflection adhesives is contributed to restrict thermal expansion of lead frame. Therefore, it is expected that the anti-deflection adhesives can be applied to lead frame packages and enhance their thermal deflection without any change of substitutive materials with low CTE.
Keywords
The semiconductor package; Thermal stress; Deflection; TSOP;
Citations & Related Records
Times Cited By KSCI : 1  (Citation Analysis)
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1 J. H. Lau, Low Cost Flip Chip Technology, pp.1-90, McGraw Hill, New York (2001).
2 J. H. Lau, Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies, pp.1-408, McGraw Hill, New York (1997).
3 D. G. Kim, J. W. Kim, J. G. Lee, H. Mori, D. J. Quesnel and S. B. Jung, "Solid State Interfacial Reaction and Joint Strength of Sn-37Pb Solder with Ni-P Under Bump Metallization in Flip Chip Application", J. Alloys Compd., 395, 80 (2005).   DOI   ScienceOn
4 J. W. Yoon, W. C. Moon and S. B. Jung, "Core Technology of Electronic Packaging", Journal of KWS, 23(2), 116 (2005).   과학기술학회마을
5 J. E. Galloway and B. M. Miles, "Moisture Absorption and Desorption Predictions for Plastic Ball Grid Array Package", IEEE Trans. Comp., Packag., Manufact. Technol. A, 20(3), 274 (1997).   DOI   ScienceOn
6 W. -L. Yang and D. M. S. Yin, "The Effects of Epoxy Molding Composition on the Warpage and Popcorn Resistance of PBGA", Proc. 49th ECTC, San Diego, 721, IEEE CPMT/EIA (1999).
7 S. Cho, H. Jung and O. Bae, "Numerical Analysis on the Design Variables and Thickness Deviation Effects on Warpage of Substrate for FCCSP" J. Microelectron. Packag. Soc., 19(3), 57 (2012).
8 S. H. Hwang, B. J. Kim, S. Y. Jung, H. Y. Lee and Y. C. Joo, "Thermo-Mechanical Analysis of Though-Silicon-Via in 3D Packaging", J. Microelectron. Packag. Soc., 17(1), 69 (2010).
9 T. K. Lee, D. M. Kim, H. I. Jun, S. W. Ha and M. Y. Jeong, "The Optimization of FCBGA Thermal Design by Micro Pattern Structure", J. Microelectron. Packag. Soc., 18(3), 59 (2011).
10 H. Ye, C. Basaran and D. C. Hopkins, "Damage Mechanics of Microelectronics Solder Joints under High Current Densities", Int. J. Solids Structures, 40, 4021 (2003).   DOI   ScienceOn