• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.423-423
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• 2004

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.509-510
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• 2016

본 논문은 계통연계형 인버터의 위상추종기법인 SRF-PLL을 모델링하고, FPGA에 구현하기 위해 System Generator를 이용하여 설계하였다. SRF-PLL의 비례-적분 이득은 소신호 해석을 하여 일반화를 통해 입력전압의 크기에 관계없이 적용가능하며, 주파수 응답에서 65도 위상여유를 갖는 안정한 이득을 산정하였다. FPGA 구현을 위해 MATLAB/SIMULINK와 연동 가능한 System Generator를 이용하여 SRF-PLL을 모델링하였으며, MATLAB 기반의 시뮬레이션과 실험을 통하여 위상추종 특성을 분석하였다.

• Proceedings of the KIPE Conference
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• 2009.11a
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• pp.302-304
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• 2009

Phase Locked Loop(PLL) 시스템은 UPS, 전력용 능동필터, PWM 정류기 등 여러 전력변환 장비에서 사용되어 왔다. 특히 계통에 연계된 능동 전력변환 시스템은 계통과의 동기화를 위해 위상각의 정확한 정보가 필요하며 PLL 시스템을 사용하여 측정한다. 실제 계통의 위상각과 추출된 위상각 사이의 오차는 기준 전류나 전압에 더 큰 고조파를 야기한다. 본 논문은 계통 고장에 강인한 PLL 시스템의 제어기를 제안한다.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.9
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• pp.562-568
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• 2004

The frequency and phase angle of the utility voltage are important in many industrial systems. In the three-phase system, they can be easily known by using the utility voltage vector. However, in the case of single phase system, there are some difficulties in detecting the information of utility voltage. In conventional system, the zero-crossing detection method is widely used, but could not obtain the information of utility voltage instantaneously. In this paper, the new digital PLL control using virtual two phase detector is proposed with a detailed analysis of single-phase digital PLL control for utility connected systems. The experimental results under various utility conditions are presented and demonstrate an excellent phase tracking capability in the single-phase grid-connected operation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07b
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• pp.1132-1135
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• 2002

In this paper, we propose a phase-locked loop (PLL) with dual loops in which advantages of both loops can be combined. Frequency-locked loop (FLL) which is composed of two frequency-to-voltage converters (FVC) and an amplifier makes the frequency synchronize very fast and output signal is synchronized in phase with the input reference signal by charge pump PLL. This structure can improve the trade-off between acquisition behavior and locked behavior.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.115-122
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• 1996

A 300MHz PLL including FVC (frequency to voltage converter) is designed and fabricated in 0.8$\mu$m CMOS process. In this design, a FVC and a 2nd - order passive filter are added to the conventional charge-pump PLL to improve the acquisition time. The dual-rijng VCO(voltage controlled oscillator) realized in this paper has a frequency range form 208 to 320MHz. Integrated circuits have been fully tested and analyzed in detail and it is proved that pull-in speed is enhanced with the use fo FVC. In VCO range from 230MHz to 310MHz, experimental results show that realized PLL exhibits 4 times faster pull-in speed than that of conventional PLL.

• Journal of IKEEE
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• v.10 no.1 s.18
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• pp.16-21
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• 2006

This paper shows a vernier delay technique for generating precise multiphase clocks using PLL structure. The proposed technique can achieve the finer timing resolution less than the gate delay of the delay chain in VCO. Using this technique, 62.5ps of timing resolution can be achieved if the reference clock rate is set at 1GHz using 0.18um CMOS technology. Jitter of 14ps peak-to-peak was measured.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.955-958
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• 1999

We designed a phase locked loop (PLL), which is applicable to microprocessor clock generation application. The designed PLL has a new simple phase frequency detector (PFD) which eliminate dead-zone and has a good high frequency characteristic. The lock-in range of the designed PLL is 50 MHz ~ 150 MHz at 3.3v power supply voltage. The design is carried out using a 0.6${\mu}{\textrm}{m}$ triple metal CMOS process. The area of the layout is 0.35mm by 0.42mm with 359 transistors.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.353-356
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• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.4
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• pp.136-141
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• 2016

A phase-locked loop(PLL) with effectively increased capacitance by current modulator has been proposed. In this paper, the effective capacitance of loop filter is increased by using current modulator and it results in 1/10 reduction of capacitance in loop filter. It has been designed with a 1.8V $0.18{\mu}m$ CMOS process. The simulation results show that the proposed PLL has the same phase noise characteristic and locking time of conventional PLL.