• 센서학회지
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• 제24권6호
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• pp.419-422
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• 2015

Pure and Mo-doped ZnO hollow nanofibers were prepared by single capillary electrospinning and their gas sensing characteristics toward 5 ppm ethanol, trimethylamine (TMA), CO and $H_2$ were investigated. The gas responses and responding kinetics were dependent upon sensing temperature and Mo doping. Mo-doped ZnO hollow nanofibers showed high response to 5 ppm TMA ($R_a/R_g=111.7$, $R_a$: resistance in air, $R_g$: resistance in gas) at $400^{\circ}C$, while the responses of pure ZnO hollow nanofibers was low ($R_a/R_g=47.1$). In addition, the doping of Mo enhanced selectivity toward TMA. The enhancement of gas response and selectivity to TMA by Mo doping to ZnO nanofibers was discussed in relation to the interaction between basic analyte gas and acidic additive materials.

• 센서학회지
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• 제24권6호
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• pp.359-363
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• 2015

This paper proposes an algorithm that reduces the conversion time of a single-slope A/D converter (SSADC) that has n-bit resolution, which typically is limited by conversion time taking up to $2^n$ clock cycles for an operation. To improve this situation, we have researched a novel hybrid-type A/D converter that consists of a pseudo-pipeline A/D converter and a conventional SSADC. The pseudo-pipeline A/D converter, using a single-stage of analog components, determines the most significant bits (MSBs) or upper bits and the conventional SSADC determines the remaining bits. Therefore, the modified SSADC, similar to the hybrid-type A/D converter, is able to significantly reduce the conversion time because the pseudo-pipeline A/D converter, which determines the MSBs (or upper bits), does not rely on a clock. The proposed A/D converter was designed using a $0.35-{\mu}m$ 2-poly 4-metal standard complementary metal oxide semiconductor (CMOS) technology process; additionally, its characteristics were simulated.

• 센서학회지
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• 제24권2호
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• pp.79-82
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• 2015

This paper proposes a novel complementary metal oxide semiconductor (CMOS) active pixel sensor (APS) and presents its performance characteristics. The proposed APS exhibits a linear-logarithmic response, which is simulated using a standard $0.35-{\mu}m$ CMOS process. To maintain high sensitivity and improve the dynamic range (DR) of the proposed APS at low and high-intensity light, respectively, two additional nMOSFETs are integrated into the structure of the proposed APS, along with a photogate. The applied photogate voltage reduces the sensitivity of the proposed APS in the linear response regime. Thus, the conversion gain of the proposed APS changes from high to low owing to the addition of the capacitance of the photogate to that of the sensing node. Under high-intensity light, the integrated MOSFETs serve as voltage-light dependent active loads and are responsible for logarithmic compression. The DR of the proposed APS can be improved on the basis of the logarithmic response. Furthermore, the reference voltages enable the tuning of the sensitivity of the photodetector, as well as the DR of the APS.

• 센서학회지
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• 제22권4호
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• pp.256-261
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• 2013

This paper presents an extension of the dynamic range in a complementary metal-oxide-semiconductor (CMOS) active pixel sensor (APS) using a stacked photodiode and feedback structure. The proposed APS is composed of two additional MOSFETs and stacked P+/N-well/P-sub photodiodes as compared with a conventional APS. Using the proposed technique, the sensor can improve the spectral response and dynamic range. The spectral response is improved using an additional stacked P+/N-well photodiode, and the dynamic range is increased using the feedback structure. Although the size of the pixel is slightly larger than that of a conventional three-transistor APS, control of the dynamic range is much easier than that of the conventional methods using the feedback structure. The simulation and measurement results for the proposed APS demonstrate a wide dynamic range feature. The maximum dynamic range of the proposed sensor is greater than 103 dB. The designed circuit is fabricated by the $0.35-{\mu}m$ 2-poly 4-metal standard CMOS process, and its characteristics are evaluated.

• 한국위성정보통신학회논문지
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• 제7권2호
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• pp.18-24
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• 2012

본 논문에서는 ESD 방지를 위한 최적 방법론에 목표하여 확장된 드레인을 갖는 EDNMOS 소자의 더블 스냅백 현상 및 백그라운 도핑 농도 (BDC)의 영향을 조사하였다. 고전류 영역에서 낮은 BDC를 가진 EDNMOS 소자는 강한 스냅백으로 인해 취약한 ESD 성능과 높은 래치업 위험을 가지게 되나, 높은 BDC를 가진 EDNMOS 소자는 스냅백을 효과적으로 방지할 수 있음을 알 수 있었다. 따라서 BDC 제어로 안정적인 ESD 방지 성능과 래치업 면역을 구현할 수 있음을 밝혔다.

• 조명전기설비학회논문지
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• 제29권2호
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• pp.8-18
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• 2015

This paper proposes a dimming method and a hybrid LED driving circuit suitable for the ultra high definition (UHD) broadcasting. There are major two problems during the dimming control for traditional LED broadcast lightings; one is a flicker that occurred when camera filming to these lightings, and the other is that linear control is impossible for LED luminous intensity under 10% due to LED electrical characteristics. The proposed dimming method and the driving circuit are designed to solve two problems simultaneously. For high level dimming control region from 10 to 100%, the analog control method was applied to the switching regulator constructed by MOSFET operated in the saturation region. For low level dimming control region under 10%, the fast PWM control method with the linear regulator constructed by MOSFET in the ohmic region was used. We verified experimentally that the dimming method is able to control the luminous intensity linearly from 1 to 100% and the flicker disappears on images taken by the charge coupled device (CCD) and the complementary metal oxide semiconductor (CMOS) cameras. Therefore, the proposed method is suitable for the UHD broadcasting.

• 한국정보통신학회논문지
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• 제6권1호
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• pp.103-108
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• 2002

MOSFET는 전력감소, 도핑농도 증가, 캐리어 속도 증가를 위해서 많은 변화를 가져왔다. 이러한 변화를 받아들이기 위해서, 채널의 길이와 공급전압이 감소해야만하며, 그것으로 인해 소자가 더욱 작아지게 되었다. 현존하고 있는 시뮬레이션 프로그램은 많은 기술자와 과학자들에 의해 개발되어졌다. 본 논문에서는 상용화되어지고 있는 두 가지 시뮬레이터인 Micro-tec과 ISE-TCAD을 사용하여 나노 구조 소자를 시뮬레이션하여 비교하였다. 소자의 게이트 길이(Lg)는 180nm를 사용하였다. 두 시뮬레이터를 사용하여 MOSFET의 특성과 I-V 곡선 및 전계에 대해서 비교 분석하였다.

• Journal of Power Electronics
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• 제13권6호
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• pp.1080-1089
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• 2013

In this paper, the superposition principle of a heat sink temperature rise is verified based on the mathematical model of a plate-fin heat sink with two mounted heat sources. According to this, the distributed coupling thermal impedance matrix for a heat sink with multiple devices is present, and the equations for calculating the device transient junction temperatures are given. Then methods to extract the heat sink thermal impedance matrix and to measure the Epoxy Molding Compound (EMC) surface temperature of the power Metal Oxide Semiconductor Field Effect Transistor (MOSFET) instead of the junction temperature or device case temperature are proposed. The new thermal impedance model for the power converters in Switched Reluctance Motor (SRM) drivers is implemented in MATLAB/Simulink. The obtained simulation results are validated with experimental results. Compared with the Finite Element Method (FEM) thermal model and the traditional thermal impedance model, the proposed thermal model can provide a high simulation speed with a high accuracy. Finally, the temperature rise distributions of a power converter with two control strategies, the maximum junction temperature rise, the transient temperature rise characteristics, and the thermal coupling effect are discussed.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.9-10
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• 2007

In this paper, Thin films of $HfO_2$/Hf were deposited on p-type wafer by Atomic Layer Deposition(ALD). And we studied the electrical characterization of $HfO_2$/Hf/Si MOS capacitor depending on thickness of Hf metal layer. $HfO_2$ films were deposited using TEMAH and $O_3\;at\;350^{\circ}C$. Samples were then annealed using furnace heating to $500^{\circ}C$. The MOS capacitor of round-type was fabricated on Si substrates. Through TEM(Transmission Electron Microscope), XRD(X-ray Diffraction), capacitance-voltage(C-V) and current-voltage(I-V) analysis, the role of thin Hf metal layer for the better $HfO_2$/Si interface property was investigated.

• Transactions on Electrical and Electronic Materials
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• 제14권2호
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• pp.71-77
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• 2013

Advanced semiconductor manufacturing technology requires methods to maximize tool efficiency and improve product quality by reducing process variability. Real-time plasma process monitoring and diagnosis have become crucial for fault detection and classification (FDC) and advanced process control (APC). Additional sensors may increase the accuracy of detection of process anomalies, and optical monitoring methods are non-invasive. In this paper, we propose the use of a chromatic data acquisition system for real-time in-situ plasma process monitoring called the Plasma Eyes Chromatic System (PECS). The proposed system was initially tested in a six-inch research tool, and it was then further evaluated for its potential to detect process anomalies in an eight-inch production tool for etching blanket oxide films. Chromatic representation of the PECS output shows a clear correlation with small changes in process parameters, such as RF power, pressure, and gas flow. We also present how the PECS may be adapted as an in-situ plasma arc detector. The proposed system can provide useful indications of a faulty process in a timely and non-invasive manner for successful run-to-run (R2R) control and FDC.