• Journal of the Korean institute of surface engineering
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• v.50 no.3
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• pp.170-176
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• 2017

EPIG (Electroless Pd/immersion Au) process was studied to replace ENIG (electroless Ni/immersion Au) and ENEPIG (electroless Ni/electroless Pd/immersion Au) processes for bump surface treatment used in high reliable flip chip packages. The palladium and gold layers formed by EPIG process were uniform with thickness of 125 nm and 34.5 nm, respectively. EPAG (Electroless Pd/autocatalytic Au) also produced even layers of palladium and gold with the thickness of 115 nm and 100 nm. TEM results exhibited that the gold layer in EPIG surface had crystalline structure while the palladium layer was amorphous one. After annealing at 250 nm, XPS analysis indicated that the palladium layer with thickness more than 22~33 nm could act as a diffusion barrier of copper interconnects. As a result of comparing the chip shear strength obtained from ENIG and EPIG surfaces, it was confirmed that the bonding strength was similar each other as 12.337 kg and 12.330 kg, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.61-71
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• 2003

Interconnect test for highly integrated environments like SoC, becomes more important as the complexity of a circuit increases. This importance is from two facts, test time and complete diagnosis. Since the interconnect test between IPs is based on the scan technology such as IEEE1149.1 and IEEE P1500, it takes long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue because a defect on interconnects are shown as a defect on a chip. But generally, interconnect test algorithms that need the short test time can not do complete diagnosis and algorithms that perform complete diagnosis need long test time. A new interconnect test algorithm is developed. The new algorithm can provide a complete diagnosis for all faults with shorter test length compared to the previous algorithms.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.89-101
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• 2006

Frequency-variant transmission line parameters are determined. Then the signal transient characterizations of frequency-dependent multi-coupled lines are investigated. With the proposed method, an accurate signal integrity degradation such as signal ringing (overshoot, undershoot) and crosstalk noises relevant to the switching patterns of signals, rising / falling time(tr, tf) and line lengths is investigated. It is shown that there may be approximately 26% discrepancy of signal transients and 260% difference of crosstalk noises between the constant RLC model and frequency-variant RLC model in on-chip global interconnects while those of package lines are 11% and 70%, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.4 no.3
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• Korean Journal of Materials Research
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• v.29 no.9
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• pp.532-541
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• 2019

Information and communication technologies are developing rapidly as IC chip size becomes smaller and information processing becomes faster. With this development, digital circuit technology is being widely applied to mobile phones, wireless LANs, mobile terminals, and digital communications, in which high frequency range of GHz is used. In high-density electronic circuits, issues of noise and EMC(Electro-Magnetic Compatibility) arising from cross talk between interconnects or devices should be solved. In this study, sheet-type electromagnetic wave absorbers that cause electromagnetic wave attenuation are fabricated using composites based on soft magnetic metal powder and silicon rubber to solve the problem of electromagnetic waves generated in wireless communication products operating at the frequency range of 2.4 GHz. Sendust(Fe-Si-Al) and carbonyl iron(Fe-C) were used as soft magnetic metals, and their concentrations and sheet thicknesses were varied. Using soft magnetic metal powder, a sheet is fabricated to exhibit maximum electromagnetic attenuation in the target frequency band, and a value of 34.2dB(99.9 % absorption) is achieved at the target frequency.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.29 no.10
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• pp.758-765
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• 2018

This paper presents a 24-GHz frequency-modulated continuous wave(FMCW) radar transceiver with two Rx and one Tx channels in 65-nm complementary metal-oxide-semiconductor(CMOS) process and implemented it on a radar system using the developed transceiver chip. The transceiver chip includes a $14{\times}$ frequency multiplier, low-noise amplifier, down-conversion mixer, and power amplifier(PA). The transmitter achieves >10 dBm output power from 23.8 to 24.36 GHz and the phase noise is -97.3 GHz/Hz at a 1-MHz offset. The receiver achieves 25.2 dB conversion gain and output $P_{1dB}$ of -31.7 dBm. The transceiver consumes 295 mW of power and occupies an area of $1.63{\times}1.6mm^2$. The radar system is fabricated on a low-loss Duroid printed circuit board(PCB) stacked on the low-cost FR4 PCBs. The chip and antenna are placed on the Duroid PCB with interconnects and bias, gain blocks and FMCW signal-generating circuitry are mounted on the FR4 PCB. The transmit antenna is a $4{\times}4$ patch array with 14.76 dBi gain and receiving antennas are two $4{\times}2$ patch antennas with a gain of 11.77 dBi. The operation of the radar is evaluated and confirmed by detecting the range and azimuthal angle of the corner reflectors.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.3
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• pp.41-47
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• 2020

The effect of Co interlayer on the interfacial reliability of SiN_x/Co/Cu thin film structure for advanced Cu interconnects was systematically evaluated by using a double cantilever beam test. The interfacial adhesion energy of the SiN_x/Cu thin film structure was 0.90 J/㎡. This value of the SiN_x/Co/Cu thin film structure increased to 9.59 J/㎡.Measured interfacial adhesion energy of SiN_x/Co/Cu structure was around 10 times higher than SiN_x/Cu structure due to CoSi₂ reaction layer formation at SiN_x/Co interface, which was confirmed by X-ray photoelectron spectroscopy analysis. The interfacial adhesion energy of SiN_x/Co/Cu structure decreased sharply after post-annealing at 200℃ for 24 h due to Co oxidation at SiN_x/Co interface. Therefore, it is required to control the CoO and Co₃O₄ formation during the environmental storage of the SiN_x/Co/Cu thin film to achieve interfacial reliability for advanced Cu interconnections.

• Journal of the Microelectronics and Packaging Society
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• v.25 no.3
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• pp.7-12
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• 2018

The effects of Ru deposition temperature and post-annealing conditions on the interfacial adhesion energies of atomic layer deposited (ALD) Ru diffusion barrier layer and Cu thin films for the advanced Cu interconnects applications were systematically investigated. The initial interfacial adhesion energies were 8.55, 9.37, $8.96J/m^2$ for the sample deposited at 225, 270, and $310^{\circ}C$, respectively, which are closely related to the similar microstructures and resistivities of Ru films for ALD Ru deposition temperature variations. And the interfacial adhesion energies showed the relatively stable high values over $7.59J/m^2$ until 250h during post-annealing at $200^{\circ}C$, while dramatically decreased to $1.40J/m^2$ after 500 h. The X-ray photoelectron spectroscopy Cu 2p peak separation analysis showed that there exists good correlation between the interfacial adhesion energy and the interfacial CuO formation. Therefore, ALD Ru seems to be a promising diffusion barrier candidate with reliable interfacial reliability for advanced Cu interconnects.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.34 no.3
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• pp.251-258
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• 2010

This paper presents the technology for the design, fabrication, and characterization of a microfluidic system interface (MSI); the purpose of this technology is to enable the integration of complex microfluidic systems. The MSI technology can be applied in a simple manner for realizing complex arrangements of microfluidic interconnects, integrated microvalves for fluid control, and optical windows for on-chip optical processes. A microfluidic system for the preparation of genetic samples was used as the test vehicle to prove the effectiveness of the MSI technology for packaging complex microfluidic systems with multiple functionalities. The miniaturized genetic sample preparation system comprised several functional compartments, including compartments for cell purification, cell separation, cell lysis, solid-phase DNA extraction, polymerase chain reaction, and capillary electrophoresis. Additionally, the functional operation of the solid-phase extraction and PCR thermocycling compartments was demonstrated by using the MSI.