• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2013.05a
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• pp.97-97
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• 2013

We present a comprehensive study on the integration of h-BN with silicon MOSFET. Temperature dependent mobility modeling is used to discern the effects of top-gate dielectric on carrier transport and identify limiting factors of the system. The result indicates that coulomb scattering and surface roughness scattering are the dominant scattering mechanisms for silicon MOSFETs at relatively low temperature. Interposing a layer of h-BN between $SiO_2$ and Si effectively weakens coulomb scattering by separating carriers in the silicon inversion layer from the charged centers as 2-dimensional h-BN is relatively inert and is expected to be free of dangling bonds or surface charge traps owing to the strong, in-plane, ionic bonding of the planar hexagonal lattice structure, thus leading to a significant improvement in mobility relative to undecorated system. Furthermore, the atomically planar surface of h-BN also suppresses surface roughness scattering in this Si MOSFET system, resulting in a monotonously increasing mobility curve along with gate voltage, which is different from the traditional one with a extremum in a certain voltage. Alternatively, high-k dielectrics can lead to enhanced transport properties through dielectric screening. Modeling indicates that we can achieve even higher mobility by using h-BN decorated $HfO_2$ as gate dielectric in silicon MOSFETs instead of h-BN decorated $SiO_2$.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.73-74
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• 2007

We fabricated strained-SOI(sSOI) n-/p-MOSFETs and investigated the electron/hole mobility characteristics. The subthreshold characteristics of sSOI MOSFETs were similar to those of conventional SOI MOSFET. However, The electron mobility of sSOI nMOSFETs was larger than that of the conventional SOI nMOSFETs. These mobility enhancement effects are attributed to the subband modulation of silicon conduction band.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.2
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• pp.115-120
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• 2008

Carrier velocity in the MOSFET channel is the main driving force for improved transistor performance with scaling. We report measurements of the drift velocity of electrons and holes in silicon inversion layers. A technique for extracting effective carrier velocity which is a more accurate extraction method based on the actual inversion charge measurement is used. This method gives more accurate result over the whole range of $V_{ds}$, because it does not assume a linear approximation to obtain the inversion charge and it does not limit the range of applicable $V_{ds}$. For a very short channel length device, the electron velocity overshoot is observed at room temperature in 37 nm MOSFETs while no hole velocity overshoot is observed down to 36 nm. The electron velocity of short channel device was found to be strongly dependent on the longitudinal field.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2002.05a
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• pp.275-278
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• 2002

As the gate lengths of MOSFETs are scaled down to sub-50nm regime, there are key issues to be considered in the device design. In this paper, we have investigated the characteristics of threshold voltage for MOSFET device. We have simulated the MOSFETs with gate lengths from 100nm to 30nm using generalized scaling. Then, we have known the device scaling limits for nano structure MOSFET. We have determined the threshold voltages using LE(Linear Extraction) method.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.317-320
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• 2001

In this paper, we have presented the simulation results about threshold voltage at Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n-channel MOSFETS with sate lengthes from 180 to 30 nm in accordance to constant voltage scaling theory. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region it due to scaling down. We investigated and analysed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.1
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• pp.109-114
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• 2002

In this paper, we have presented the simulation results ah)ut threshold voltage for Si-based MOSFETs with channel length of nano scale. We simulated the Si-based n channel MOSFETs with gate lengths from 180 to 30 nm in accordance to the constant voltage scaling theory and the lateral scaling. These MOSFETs had the lightly doped drain(LDD) structure, which is used for the reduction of electric field magnitude and short channel effects at the drain region. The stronger electric field at this region is due to scaling down. We investigated and analyzed the threshold voltage of these devices. This analysis will provide insight into some applicable limitations at the ICs and used for basis data at VLSI.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.579-580
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• 2006

Simple nonoverlapped source/drain-to-gate MOSFETs to suppress GIDL (gate-induced drain leakage) is simulated with SILVACO simulation tool. Changing spacer thickness for adjusting length of Drain to Gate nonoverlapped region, this simulation observes on/off characteristic of nonoverlapped source/drain-to-gate MOSFETs. Off current is dramatically decreased with S/D to gate nonoverlapped length increasing. The result shows that maximum on/off current ratio is achieved by adjusting nonoverlapped length.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.1-8
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• 2005

The gate length-dependence of cutoff frequency is modeled by using scaling parameter equations of equivalent circuit parameters extracted from measured S-parameters of Nano-scale MOSFETs. It is observed that the modeled cutoff frequency initially increases with decreasing gate length and then the rate of increase becomes degraded at further scale-down. This is because the extrinsic charging time slightly decreases, although the intrinsic transit time greatly decreases with gate length reduction. The new gate length-dependent model will be very helpful to optimize RF performances of Nano-scale MOSFETs.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.611-614
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• 2005

In this paper, investigated is the relationship between the formation temperature and the thermal stability of Ni silicide formed with Ni-V (Nickel Vanadium) alloy target. The sheet resistance after the formation of Ni silicide with the Ni-V showed stable characteristic up to RTP temperature of $700\;^{\circ}C$ while degradation of sheet resistance started at that temperature in case of pure-Ni. Moreover, the Ni silicide with Ni-V indicated more thermally stable characteristic after the post-silicidation annealing. It is further found that the thermal robustness of Ni silicide with Ni-V was highly dependent on the formation temperature. With the increased silicidation temperature (around $700\;^{\circ}C$), the more thermally stable Ni silicide was formed than that of low temperature case using the Ni-V.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.15-16
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• 2006

The thermal stability of nickel silicide with compressively and tensilely stressed nitride capping layer has been investigated in this study. The Ni (10 nm) and Ni/Co/TiN (7/3/25 nm) structures were deposited on the p-type Si substrate. The stressed capping layer was deposited using plasma enhanced chemical vapor deposition (PECVD) after silicide formation by one-step rapid thermal process (RTP) at $500^{\circ}C$ for 30 sec. It was found that the thermal stability of nickel silicide depends on the stress induced by the nitride capping layer. In the case of Ni (10 nm) structure, the high compressive sample shows the best thermal stability, whereas in the case of Ni/Co/TiN (7/3/25 nm) structure, the high compressive sample shows the worst thermal stability.