• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.775-777
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• 2016

In this paper presents an analysis of pulsed radiation effects of unit devices. Unit devices are the nMOSFET, pMOSFET, NPN Transistor and those fabricated by the 0.18um CMOS process. Pulsed radiation test results in nMOSFET, the photocurrent of tens nA was generated in $2.07{\times}10^8rad(si)/s$. For the pMOSFET, a photocurrent generation was not observed in $3{\times}10^8rad(si)/s$. For the NPN transistor, the photocurrent was generated with about 1uA. Therefore, the MOSFET must be used than BJT transistor when radhard IC design.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.54-59
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• 2008

A highly accurate wide swing BiCMOS cascode current mirror is proposed. It uses the base-current compensated BJT current mirror. It increases both output impedance and output voltage range by using the npn-NMOS cascode instead of the NMOS-NMOS cascode. The npn transistor copies the input current and the NMOS transistor increases the output impedance for the accurate current mirroring. The proposed current mirror achieves highly constant current for wide output voltage range. Simulation results were verified with measurements performed on a fabricated chip using a 5/16V 0.5um BCD process. It has only $-2.5%{\sim}1.0%$ current error for $0.3V{\sim}16V$ output voltage range.

• Journal of IKEEE
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• v.23 no.1
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• pp.338-341
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• 2019

In this paper, we propose a novel ESD device with improved characteristics of LVTSCR, which is a representative ESD protection device, and verify the N-stack technology for design optimized for each required voltage of a specific application. The characteristics of the holding voltage and the trigger voltage, which are the main parameters, are examined and the temperature characteristic, which is an indicator of the tolerance characteristic, is also verified. well region and a parasitic NPN to form a series-connected structure. We used synopsys' T-cad simulation tool for characterization.

• Journal of IKEEE
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• v.26 no.3
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• pp.520-523
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• 2022

In this paper, an ESD protection device with a simpler structure than the existing ESD protection device is proposed. The proposed new structure operates an additional NPN parasitic bipolar transistor by adding an N+ diffusion region and connecting it to the bridge region, thereby lowering the current gain. As a result, it was confirmed that the proposed ESD protection device has a trigger voltage of 10.8V and a holding voltage of 6.1V. It is expected to have reliability for 5V applications and is expected to have high tolerance characteristics.

• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.5
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• pp.51-56
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• 1995

The transistors of single phase 3 level PWM Inverter compose output power transistors and neutral point clamping transistors, which are NPN transistors. Waveforms of driving signals for this are PWM waves for power transistors and period operating waves for neutral point clamping transistors, which signals made W-type modulation from rectangular and sine wave. The output power transistors operate at ON-time complementary and neutral point clamping transistors operate at OFF-time complementary respectively. Therefore, each transistors operate in half period at parallel. Characteristics of this inverter circuit is parallel switching method about series switching method of general inverter. As modulation of 3 level drive signals made from full-wave rectifier of sine wave and rectangular wave, which are level wave about 3 level of complementary transistor inverter. So, this circuit composed complementary operation inverter of NPN transistors only compare with PNP-NPN complementary inverter, which have high power 3 level inverter of complementary operation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.11a
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• pp.151-154
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• 1998

기존의 바이폴라 논리회로에서 신호변환시 베이스 영역의 소수 캐리어를 빨리 제거하기 위해서, 베이스 부분의 매몰층을 줄여서 npn트랜지스터의 베이스와 에피층과 기판사이에 병합 pnp 트랜지스터를 생성한 트랜지스터와 게이트 당 전달 지연 시간을 측정하기 위한 링-발진기를 설계, 제작하였다. 게이트의 구조는 수직 npn 트랜지스터와 기판과 병합 pnp 트랜지스터이다. 결과로서 npn 트랜지스터의 에미터의 면적이 기존의 접합넓이에 비해서 상당히 적기 때문에 에미터에서 진성베이스로 유입되는 캐리어와 가장자리 부분으로 유입되는 캐리어가 상대적으로 많기 때문에 이 많은 양은 결국 베이스의 전류가 많이 헝성되며, 또 콜렉터의 매몰층이 거의 반으로 줄었기 때문에 콜렉터 전류가 적게 형성되어 이득이 낮아진다. 병합 pnp 트랜지스터는 베이스폭이 크고 농도 분포에서 에미터의 농도와 베이스의 농도 차이가 적기 때문에 전류 이득이 낮아졌다. 게이트를 연결하여 링-발진기를 제작하여 측정한 AC특성의 출력은 정현파로 논리전압의 진폭은 200mV, 최소 전달 지연시간은 211nS이며, 게이트당 최소 전달지연 시간은 7.26nS의 개선된 속도 특성을 얻었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.27 no.3
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• pp.167-171
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• 2014

This paper examines the destruction behavior of NPN BJT (bipolar junction transistor) by repetition pulse. The injected pulse has a rise time of 1 ns and the maximum peak voltage of 2 kV. Pulse was injected into the base of transistor. Transistor was destroyed, current flows even when the base power is turned off. Cause the destruction of the transistor is damaged by heat. Breakdown voltage of the transistor is 975 V at single pulse, and repetition pulse is 525~575 V. Pulse repetition rate increases, the DT (destruction threshold) is reduced. Pulse Repetition rate is high, level of transistor destruction is more serious.

• Journal of IKEEE
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• v.28 no.3
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• pp.360-364
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• 2024

Npn heterostructures with GaN collectors were fabricated using nanomembrane (NM) stacking. N- and p-Si NMs were transfer-printed onto the n-GaN substrates, resulting in the formation of vertical n-Si/p-Si/n-GaN heterostructures. Electrical measurements of Si/Si and Si/GaN pn heterostructures exhibited rectifying properties, indicating that the formation of bipolar junctions was feasible through NM stacking. The energy band diagram of stacking-enabled npn heterostructure was analyzed to explain the rectifying behaviors of base-emitter and collector-base junctions, as well as to suggest potential applications for bipolar junction transistors with a GaN subcollector.

• Korean Journal of Optics and Photonics
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• v.6 no.2
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• pp.93-100
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• 1995

3구면경계에서 aplanat 조건을 해석적으로 유도하고 이를 바탕으로 3종의 3차수차가 보정된 3구면 경계의 형태 및 존재영역을 조사하였다. 실상을 맺으면서 aplanat 저건을 만족하는 3구면경계는 유효초점거리가 양수인 경우 PPN, NPP, PNP 형태의 해가 존재하였으며 N은 볼록 거울, P는 오목 거울을 나타낸다. 유효초점거리가 음수인 경우 NPN, NPP, PNP, NNP형의 4종류의 형태가 존재하였다. 3종의 3차수차가 보정된 3구면경계에서 astigmatic aplanat는 실상을 맺는 해가 존재하지 않았다. Flat field aplanat는 PPN, PNP, NPP형태의 해가 존재하였고 distortion free aplanat의 경우는 PPN, PNP, NPN, NPP, NNP형의 해가 존재하였다.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.1338-1341
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• 1993

We present here two Petri nets formalisms that can deal with uncertainty by the use of necessity-valued logic. The first and basic model, called necessity-valued Petri nets (NPN), can at the same time deal with uncertainty on markings are on transitions. The second model, called necessity-valued Petri nets (TNPN), is an extension of both NPN and timed Petri nets.