• 제목/요약/키워드: Multilevel Cascaded Inverter

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Unification of Buck-boost and Flyback Converter for Driving Cascaded H-bridge Multilevel Inverter with Single Independent DC Voltage Source

  • Kim, Seong-Hye;Kim, Han-Tae;Park, Jin-Soo;Kang, Feel-Soon
    • Journal of international Conference on Electrical Machines and Systems
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    • 제2권2호
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    • pp.190-196
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    • 2013
  • It presents a unification of buck-boost and flyback converter for driving a cascaded H-bridge multilevel inverter with a single independent DC voltage source. Cascaded H-bridge multilevel inverter is useful to make many output voltage levels for sinusoidal waveform by combining two or more H-bridge modules. However, each H-bridge module needs an independent DC voltage source to generate multi levels in an output voltage. This topological characteristic brings a demerit of increasing the number of independent DC voltage sources when it needs to increase the number of output voltage levels. To solve this problem, we propose a converter combining a buck-boost converter with a flyback converter. The proposed converter provides independent DC voltage sources at back-end two H-bridge modules. After analyzing theoretical operation of the circuit topology, the validity of the proposed approach is verified by computer-aided simulations using PSIM and experiments.

A New Design for Cascaded Multilevel Inverters with Reduced Part Counts

  • Choupan, Reza;Nazarpour, Daryoush;Golshannavaz, Sajjad
    • Transactions on Electrical and Electronic Materials
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    • 제18권4호
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    • pp.229-236
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    • 2017
  • This paper deals with the design and implementation of an efficient topology for cascaded multilevel inverters with reduced part counts. In the proposed design, a well-established basic unit is first developed. The series extension of this unit results in the formation of the proposed multilevel inverter. The proposed design minimizes the number of power electronic components including insulated-gate bipolar transistors and gate driver circuits, which in turn cuts down the size of the inverter assembly and reduces the operating power losses. An explicit control strategy with enhanced device efficiency is also acquired. Thus, the part count reductions enhance not only the economical merits but also the technical features of the entire system. In order to accomplish the desired operational aspects, three algorithms are considered to determine the magnitudes of the dc voltage sources effectively. The proposed topology is compared with the conventional cascaded H-bridge multilevel inverter topology, to reflect the merits of the presented structure. In continue, both the analytical and experimental results of a cascaded 31-level structure are analyzed. The obtained results are discussed in depth, and the exemplary performance of the proposed structure is corroborated.

Cascaded H-bridge PWM 멀티레벨인버터의 스위칭 손실 저감을 위한 효율적인 스위칭 패턴 (Efficient Switching Pattern to Decrease Switching Losses in Cascaded H-bridge PWM Multilevel Inverter)

  • 정보창;김선필;김광수;박성준;강필순
    • 전기학회논문지
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    • 제62권4호
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    • pp.502-509
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    • 2013
  • It presents an efficient switching pattern, which expects a reduction of switching losses in a cascaded H-bridge PWM multilevel inverter. By the proposed switching scheme, the lower H-bridge module operates at low frequency of 60[Hz] because it assigns to transfer most load power. The upper H-bridge module operates at high frequency of PWM switching to improve THD of output voltage. The proposed switching pattern applies to cascaded H-bridge multilevel inverter with PD, APOD, bipolar, and unipolar switching methods. By computer-aided simulations, we verify the validity of the proposed switching scheme. Finally, we prove that the proposed PD and APOD switching patterns are better than those of the conventional one in efficiency.

Hybrid Cascaded MLI topology using Ternary Voltage Progression Technique with Multicarrier Strategy

  • Venugopal, Jamuna;Subarnan, Gayathri Monicka
    • Journal of Electrical Engineering and Technology
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    • 제10권4호
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    • pp.1610-1620
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    • 2015
  • A major problem in conventional multilevel inverter is that an increase in power semiconductor switches causes an increase in cost and switching losses of the inverter. The multicarrier strategy adopted for the multilevel inverters has become more popular due to reduced cost, lower harmonic distortion, and higher voltage capability than the conventional switching strategy applied to inverters. Various topologies and modulation strategies have been reported for utility and drive applications. Level shifted based pulse width modulation techniques are proposed to investigate the performance of the multilevel inverter. The proposed work focuses on reducing the utilized switches so that the cost and the switching losses of the inverter do not go up and the consistent efficiency could be achieved. This paper presents the detailed analysis of these topologies. The analysis is based on the number of switches, DC sources, output level, maximum voltage, and the efficiency. As an illustration, single phase cascaded multilevel inverter topologies are simulated using MATLAB/SIMULINK and the experimental results demonstrate the viability of these inverters.

Development of a Switched Diode Asymmetric Multilevel Inverter Topology

  • Karthikeyan, D.;Krishnasamy, Vijayakumar;Sathik, Mohd. Ali Jagabar
    • Journal of Power Electronics
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    • 제18권2호
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    • pp.418-431
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    • 2018
  • This paper presents a new asymmetrical multilevel inverter with a reduced number of power electronic components. The proposed multilevel inverter is analyzed using two different configurations: i) First Configuration (with a switched diode) and ii) Second Configuration (without a switched diode). The presented topologies are compared with recent multilevel inverter topologies in terms of number of switches, gate driver circuits and blocking voltages. The proposed topologies can be cascaded to generate the maximum number of output voltage levels and they are suitable for high voltage applications. Various power quality issues are addressed for both of the configurations. The proposed 11-level inverter configuration is simulated using MATLAB and it is validated with a laboratory based experimental setup.

A Single-Phase Cell-Based Asymmetrical Cascaded Multilevel Inverter

  • Singh, Varsha;Pattnaik, Swapnajit;Gupta, Shubhrata;Santosh, Bokam
    • Journal of Power Electronics
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    • 제16권2호
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    • pp.532-541
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    • 2016
  • A single-phase asymmetrical cascaded multilevel inverter is introduced with the goal of increasing power quality with the reduction of power in insulated-gate bipolar transistor (IGBT) switches. In the present work, the proposed inverter topology is analyzed and generalized with respect to different proposed algorithms for choosing different voltage source values. To prove the advantages of the proposed inverter, a case study involving a 17-level inverter is conducted. The simulation and experimental results with reduced THD are also presented and compared with the MATLAB/SIMULINK simulation results. Finally, the proposed topology is compared with different multilevel inverter topologies available in the literature in terms of the number of IGBT switches required with respect to the number of levels generated in the output of inverter topologies.

고조파 저감을 위한 다중 레벨 PWM 인버터 (A multilevel PWM Inverter for Harmonics Reduction)

  • 강필순;박성준;김철우
    • 대한전기학회논문지:전기기기및에너지변환시스템부문B
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    • 제51권11호
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    • pp.645-651
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    • 2002
  • In this paper, a multilevel PWM inverter employing a cascaded transformer is presented to reduce the harmonics of output voltage and load currents. The proposed PWM inverter consists of two full-bridge modules and their corresponding transformers. The secondarics of each transformer are series-connected. So continuous output voltage levels can be synthesized from the suitable selection of the turns ratio of trasformer. And it appears an integral ratio to input DC source. Because of the cascaded connection of transformers, output filter inductor is not necessary. The operational principles and analysis are explained, and it is compared with a conventional isolated H-bridge PWM inverter. The validity of proposed multilevel inverter is verified through simulated and experimental waveform and their FFT results.

모델 예측 제어 기반 Cascaded H-bridge 컨버터의 균일한 손실, 스위칭 주파수, 전력 분배를 위한 알고리즘 (An Algorithm for Even Distribution of Loss, Switching Frequency, Power of Model Predictive Control Based Cascaded H-bridge Multilevel Converter)

  • 김이김;곽상신
    • 전력전자학회논문지
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    • 제20권5호
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    • pp.448-455
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    • 2015
  • A model predictive control (MPC) method without individual PWM has been recently researched to simplify and improve the control flexibility of a multilevel inverter. However, the input power of each H-bridge cell and the switching frequency of switching devices are unbalanced because of the use of a restricted switching state in the MPC method. This paper proposes a control method for balancing the switching patterns and cell power supplied from each isolated dc source of a cascaded H-bridge inverter. The supplied dc power from isolated dc sources of each H-bridge cells is balanced with the proposed cell balancing method. In addition, the switching frequency of each switching device of the CHB inverter becomes equal. A simulation and experimental results are presented with nine-level and five-level three-phase CHB inverter to validate the proposed balancing method.

A Fault Diagnosis Method in Cascaded H-bridge Multilevel Inverter Using Output Current Analysis

  • Lee, June-Hee;Lee, June-Seok;Lee, Kyo-Beum
    • Journal of Electrical Engineering and Technology
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    • 제12권6호
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    • pp.2278-2288
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    • 2017
  • Multilevel converter topologies are widely used in many applications. The cascaded H-bridge multilevel inverter (CHBMI), which is one of many multilevel converter topologies, has been introduced as a useful topology in high and medium power. However, it has a drawback to require a lot of switches. Therefore, the reliability of CHBMI is important factor for analyzing the performance. This paper presents a simple switch fault diagnosis method for single-phase CHBMI. There are two types of switch faults: open-fault and short-fault. In the open-fault, the body diode of faulty switch provides a freewheeling current path. However, when the short-fault occurs, the distortion of output current is different from that of the open-fault because it has an unavailable freewheeling current flow path due to a disconnection of fuse. The fault diagnosis method is based on the zero current time analysis according to zero-voltage switching states. Using the proposed method, it is possible to detect the location of faulty switch accurately. The PSIM simulation and experimental results show the effectiveness of proposed switch fault diagnosis method.

A Flyback-Assisted Single-Sourced Photovoltaic Power Conditioning System Using an Asymmetric Cascaded Multilevel Inverter

  • Manoharan, Mohana Sundar;Ahmed, Ashraf;Park, Joung-Hu
    • Journal of Power Electronics
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    • 제16권6호
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    • pp.2272-2283
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    • 2016
  • This paper proposes a power conditioning system (PCS) for distributed photovoltaic (PV) applications using an asymmetric cascaded multilevel inverter with a single PV source. One of the main disadvantages of the cascaded multilevel inverters in PV systems is the requirement of multiple isolated DC sources. Using multiple PV strings leads to a compromise in either the voltage balance of individual H-bridge cells or the maximum power point tracking (MPPT) operation due to localized variations in atmospheric conditions. The proposed PCS uses a single PV source with a flyback DC-DC converter to facilitate a reduction of the required DC sources and to maintain the voltage balance during MPPT operation. The flyback converter is used to provide input for low-voltage H-bridge cells which processes only 20% of the total power. This helps to minimize the losses occurring in the proposed PCS. Furthermore, transient analyses and controller design for the proposed PCS in both the stand-alone mode and the grid-connection mode are presented. The feasibility of the proposed PCS and its control scheme have been tested using a 1kW hardware prototype and the obtained results are presented.