Journal of Power Electronics

  • 제18권2호
  • /
  • Pages.418-431
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  • 2018
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  • 1598-2092(pISSN)
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  • 2093-4718(eISSN)
전력전자학회 (The Korean Institute of Power Electronics)
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Development of a Switched Diode Asymmetric Multilevel Inverter Topology

  • Karthikeyan, D. (Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology) ;
  • Krishnasamy, Vijayakumar (Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology) ;
  • Sathik, Mohd. Ali Jagabar (Department of Electrical and Electronics Engineering, SRM Institute of Science and Technology)
  • 투고 : 2017.01.30
  • 심사 : 2017.10.18
  • 발행 : 2018.03.20
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⟨ 이전 논문 다음 논문 ⟩

초록

This paper presents a new asymmetrical multilevel inverter with a reduced number of power electronic components. The proposed multilevel inverter is analyzed using two different configurations: i) First Configuration (with a switched diode) and ii) Second Configuration (without a switched diode). The presented topologies are compared with recent multilevel inverter topologies in terms of number of switches, gate driver circuits and blocking voltages. The proposed topologies can be cascaded to generate the maximum number of output voltage levels and they are suitable for high voltage applications. Various power quality issues are addressed for both of the configurations. The proposed 11-level inverter configuration is simulated using MATLAB and it is validated with a laboratory based experimental setup.

키워드

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Fig. 1. Basic unit of the proposed multilevel inverter.

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Fig. 2. Various modes of operation for the proposed 11-level inverter.

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Fig. 3. Proposed multilevel inverter without a switched diode.

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Fig. 4. Proposed cascaded multilevel inverter topology.

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Fig. 5. Voltage balancing circuits: (a) for an unregulated dcsource (b) for a regulated dc source.

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Fig. 6. Pulse generation waveform for an 11-level inverter with a DC-link capacitor discharging period.

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Fig. 7. Different multilevel inverter topologies with a reduced switch count.

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Fig. 8. Various comparison results: (a) NLevel Vs NSwicthes; (b)NLevel Vs NSources; and (c) NLevel Vs TSV.

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Fig. 9. Voltage waveform across the diode and switch: (a) simulation results; (b) experimental results.

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Fig. 10. Simulation results of: (a) the first configuration output voltage and current waveform with a FFT spectrum; (b) the secondconfiguration output voltage and current waveform with a FFT Spectrum.

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Fig. 11. (a) Balanced input voltage by balancing the circuits; and (b) blocking voltage across various switches in an 11-levelinverter.

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Fig. 12. Output voltage and current waveforms of switched-diode configuration.

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Fig. 13. Experimental results of a switched-diode with a voltage FFT spectrum and power quality analyzer output.

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Fig. 14. Output voltage and current waveforms of the second configuration.

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Fig. 15. Experimental results of the second configuration with a voltage FFT spectrum and power quality analyzer output.

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Fig. 16. Photograph of the experimental model.

TABLE I SWITCHING SEQUENCE FOR THE PROPOSED 11-LEVEL INVERTER

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TABLE II COMPARISON OF THE PROPOSED TOPOLOGY IN TERMS OF THE FUNDAMENTAL MODULE AND THE NUMBER OF LEVELS

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TABLE III COMPARISONS OF DIFFERENT MULTILEVEL INVERTER TOPOLOGIES FOR VARIOUS PARAMETERS

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TABLE IV SUMMARY OF BOTH CONFIGURATIONS OF THE PROPOSED TOPOLOGY

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