• ETRI Journal
• /
• v.32 no.1
• /
• pp.1-10
• /
• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.54 no.7
• /
• pp.29-35
• /
• 2017

This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.17 no.1
• /
• pp.101-109
• /
• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.6 no.4
• /
• pp.243-248
• /
• 2011

A FFT/IFFT processor is the key component for orthogonal frequency division multiplexing (OFDM) systems based IEEE 802.11n wireless local area network (WLAN). There exists many radix algorithms according to the structure of butterfly as FFT sub-module, each has the pros and cons on hardware complexity. Here, mixed radix algorithms for 64 and 128 FFT/IFFT processors are proposed, which reduce hardware complexity by using mixture of radix-23 and radix-4 algorithms. The proposed algorithm finish calculation within 3.2${\mu}s$ in order to meet IEEE 802.11n standard requirements and it has less hardware complexity compared with conventional algorithms.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.9
• /
• pp.454-460
• /
• 2003

In this paper, we present a novel method of parallelization of the modular multiplication algorithm to improve time and space complexity on RNS (Residue Number System). The parallel algorithm executes modular reduction using new table lookup based reduction method. MRS (Mixed Radix number System) is used because algebraic comparison is difficult in RNS which has a non-weighted number representation. Conversion from residue number system to certain MRS is relatively fast in residue computer. Therefore magnitude comparison is easily Performed on MRS. By the analysis of the algorithm, it is known that it requires only 1/2 table size than previous approach. And it requires 0(ι) arithmetic operations using 2ㅣ processors.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.32 no.10C
• /
• pp.1025-1031
• /
• 2007

This paper proposes an area-efficient pipeline FFT processor for MIMO-OFDM systems with four transmitting and four receiving antennas. Since the MIMO-OFDM system transmits multiple data streams, the complexity for the MIMO-OFDM system with a single-channel FFT processor increases linearly with the increase of the number of transmit channels. The proposed FFT processor is based on multi-channel structure, and therefore it can efficiently support multiple data streams. With the mixed radix algorithm, the number of non-trivial multiplications of the proposed FFT processor is decreased. The proposed FFT processor is synthesized with CMOS $0.18{\mu}m$ process and reduces the logic gates by 25% over a 4-channel Radix-4 multi-path delay commutator (R4MDC) FFT processor. Since the MIMO-OFDM FFT processor is one of the largest modules in the systems, the proposed FFT processor will be a vast contribution improvement to the low complexity design of MIMO-OFDM systems.

• Electronics and Telecommunications Trends
• /
• v.37 no.1
• /
• pp.53-62
• /
• 2022

With increasing size of transformer-based neural networks, a light-weight algorithm and efficient AI accelerator has been developed to train these huge networks in practical design time. In this article, we present a survey of state-of-the-art research on the low-precision computational algorithms especially for floating-point formats and their hardware accelerator. We describe the trends by focusing on the work of two leading research groups-IBM and Seoul National University-which have deep knowledge in both AI algorithm and hardware architecture. For the low-precision algorithm, we summarize two efficient floating-point formats (hybrid FP8 and radix-4 FP4) with accuracy-preserving algorithms for training on the main research stream. Moreover, we describe the AI processor architecture supporting the low-bit mixed precision computing unit including the integer engine.

• The Transactions of the Korea Information Processing Society
• /
• v.3 no.1
• /
• pp.55-62
• /
• 1996

MRNS network is a general algebraic structure of Hypercube network which has recently drawn considerable attention to supercomputing and message-passing communication. In this paper, we investigate the routing of a message in an n- dimensional MRNS network that is a key to the performance of this network. On the n-dimensional MRNS network we would like to transmit packets from a source node to a destination node simultaneously along a fixed number of paths, where the superscript packet will traverse along the superscript path. In order for all packets to arrive at the destination node quickly and securely, the ith path must be node-disjoint from all other paths. By investigating the conditions of node-disjoint paths, we will employ the special matrices called as the Hamiltonian Circuit Latin Square(HCLS) described in 〔1〕to construct a set of node-disjoint paths and suggest a linear-time parallel routing algorithm for the MRNS network.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.10a
• /
• pp.621-622
• /
• 2017

In this paper, a low-complexity FFT processor is proposed for narrow-band interference signal cancellation based array antenna. The proposed FFT pocessor can support the variable length of 64, 128 and 512. By reducing number of non-tirval multipliers with mixed radix-4/2/4/2/4/2 algorithm and flexible multi-path delay commutator(MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased. The proposed FFT processor was designed in Xilinx system generator and Implemented with Xilinx Virtex-7 FPGA. With the proposed architecture, the number of slices for the processor is 11454, and the number of DSP48s is 194.

• Journal of the Korea Institute of Information Security & Cryptology
• /
• v.7 no.3
• /
• pp.105-116
• /
• 1997

Routing security is related to the confidentiality of the route taken by the data transmitted over the network. If the route is detected by the adversary, the probability is higher that the data are lost or the data can be intercepted by the adversary. Therefore, the route must be protected. To accomplish this, we select an intermediate node secretly and transmit the data using this intermediate node, instead of sending the data to the destination node using the shortest path. Furthermore, if we use a number of secret routes from the starting node to the destination node, data security is much stronger since we can transmit partial data rather than the entire data along a secret route. In this paper, the routing algorithm for multiple secret paths on MRNS(Mixed Radix Number System) Network, which requires O(1) for the time complexity where is the number of links on a node, is presented employing the HCLS(Hamiltonian Circuit Latin Square) and is analyzed in terms of entropy.