• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.41.2-41.2
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• 2011

Recently, scaling down of ULSI (Ultra Large Scale Integration) circuit of CMOS (Complementary Metal Oxide Semiconductor) based electronic devices become much faster speed and smaller size than ever before. However, very narrow interconnect line width causes some drawbacks. For example, deposition of conformal and thin barrier is not easy moreover metallization process needs deposition of diffusion barrier and glue layer. Therefore, there is not enough space for copper filling process. In order to overcome these negative effects, simple process of copper metallization is required. In this research, Cu-V thin alloy film was formed by using RF magnetron sputter deposition system. Cu-V alloy film was deposited on the plane $SiO_2$/Si bi-layer substrate with smooth and uniform surface. Cu-V film thickness was about 50 nm. Cu-V layer was deposited at RT, 100, 150, 200, and $250^{\circ}C$. XRD, AFM, Hall measurement system, and XPS were used to analyze Cu-V thin film. For the barrier formation, Cu-V film was annealed at 200, 300, 400, 500, and $600^{\circ}C$ (1 hour). As a result, V-based thin interlayer between Cu-V film and $SiO_2$ dielectric layer was formed by itself with annealing. Thin interlayer was confirmed by TEM (Transmission Electron Microscope) analysis. Barrier thermal stability was tested with I-V (for measuring leakage current) and XRD analysis after 300, 400, 500, 600, and $700^{\circ}C$ (12 hour) annealing. With this research, over $500^{\circ}C$ annealed barrier has large leakage current. However V-based diffusion barrier annealed at $400^{\circ}C$ has good thermal stability. Thus, thermal stability of vanadium-based thin interlayer as diffusion barrier is good for copper interconnection.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.112-117
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• 2008

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.246-246
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• 2010

As the trench width in the interconnect technology decreases down to nano-scale below 50 nm, superconformal gap-filling process of Cu becomes very critical for Cu interconnect. Obtaining superconfomral gap-filling of Cu in the nano-scale trench or via hole using MOCVD is essential to control nucleation and growth of Cu. Therefore, nucleation of Cu must be suppressed near the entrance surface of the trench while Cu layer nucleates and grows at the bottom of the trench. In this study, suppression of Cu nucleation was achieved by treating the Ru barrier metal surface with capacitively coupled hydrogen plasma. Effect of hydrogen plasma pretreatment on Cu nucleation was investigated during MOCVD on atomic-layer deposited (ALD)-Ru barrier surface. It was found that the nucleation and growth of Cu was affected by hydrogen plasma treatment condition. In particular, as the plasma pretreatment time and electrode power increased, Cu nucleation was inhibited. Experimental data suggests that hydrogen atoms from the plasma was implanted onto the Ru surface, which resulted in suppression of Cu nucleation owing to prevention of adsorption of Cu precursor molecules. Due to the hydrogen plasma treatment of the trench on Ru barrier surface, the suppression of Cu nucleation near the entrance of the trenches was achieved and then led to the superconformal gap filling of the nano-scale trenches. In the case for without hydrogen plasma treatments, however, over-grown Cu covered the whole entrance of nano-scale trenches. Detailed mechanism of nucleation suppression and resulting in nano-scale superconformal gap-filling of Cu will be discussed in detail.

• ETRI Journal
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• v.17 no.2
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• pp.21-30
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• 1995

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a one-time, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below $20{\Omega}$. The chip has been fabricated using a $0.8-{\mu}m$ n-well complementary metal oxide semiconductor technology with two layers of metalization.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.34D no.12
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• pp.76-82
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• 1997

Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily ahieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etch-back process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurment of planarity. mOreover, it will contribute to analyze planarization characteristics and establish CMP model.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1996.11a
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• pp.167-171
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• 1996

Chemical mechanical polishing (CMP) has become widely accepted for the planarization of multi-interconnect structures in semiconductor manufacturing. However, perfect planarization is not so easily achieved because it depends on the pattern sensitivity, the large number of controllable process parameters, and the absence of a reliable process model, etc. In this paper, we realized the planarization of deposited oxide layers followed by metal (W) polishing as a replacement for tungsten etchback process for via formation. Atomic force microscope (AFM) is used for the evaluation of pattern topography during CMP. As a result, AFM evaluation is very attractive compared to conventional methods for the measurement of planarity. Moreover, it will contribute to analyze planarization characteristics and establish CMP model.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.49 no.8
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• pp.433-437
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• 2000

We fabricated switch module of ATM(Asynchronous Transfer Mode) exchange system with MCM-C(MultiChip Module Co-fired) technology and measured its electrical characteristics. Green tape was used as substrate and Au/Ag paste was used to form the interconnect layers. The via holes were made by drill and filled with metal paste usign screen method. After manufacturing the substrate, chips and passive components were assembled on the substrate. In electrical test, the module showed the output signal of 46.9MHz synchronized with input signal. In the view of substrate size reduction, the area of MCM switch module was 35% of conventional hybrid switch module.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.356-356
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• 2013

Monolithic 3D-IC는 현대 집적회로에서 interconnect로 인해 발생되는 여러 문제들을 해결하기 위해 새롭게 제시되고 있는 기술적 개념으로 구현 시 하위 소자 및 interconnet들에 영향을 주지 않는 저온공정이 필수적이다. 특히 germanium (Ge)은 낮은 녹는점 및 높은 캐리어 이동도 덕분에 3D-IC 구현 시 상위 소자의 channel 물질에 적합한 것으로 알려져 있다. 최근 이러한 Ge을 결정화하기 위해 solid phase crystallization (SPC), metal induced crystallization (MIC), laser annealing과 같은 결정화 방법들이 보고되고 있다. 현재까지 SPC 방법에 의해 얻어진 poly-Ge의 도핑농도 및 이동도와 같은 전기적 특성에 대한 분석은 수행된 바 있으나 3D-IC 공정에 적용이 가능한 MIC 기술을 통해 얻어진 poly Ge 필름에 대한 전기적 특성분석은 부족한 상황이다. 본 연구는 SPC 뿐만 아니라 MIC 방법을 통해 ${\alpha}$-Ge를 결정화시키고 얻어진 poly-Ge 필름의 전기적 특성을 XRD 및 hall effect measurement를 통해 분석하였다. 특히 일반적으로 Ge 내에서 p-type dopant로 동작을 하는 defect과 n-type dopant인 phosphorus 관계를 고려하여 여러 온도에서 SPC 및 MIC에 의해 얻어진 phosphorus doped poly-Ge 필름들의 전기적 특성을 분석하였다.

• Journal of Korea Society of Industrial Information Systems
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• v.18 no.1
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• pp.19-24
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• 2013

As CMOS technology is scaled down more aggressively, the reliability mechanism (or aging effect) caused by the diffusion of metal atoms along the conductor in the direction of the electron flow, also called electromigration (EM), has become a major reliability concern. With the present of EM, it is difficult to control the current flows of the MOSFET device and interconnect. In addition, nanoscale CMOS circuits suffer from increased gate leakage current and power consumption. In this paper, the EM effects on current of the nanoscale CMOS circuits are analyzed. Finally, this paper introduces an on-chip current measurement method providing lifetime electromigration management which are designed using 45-nm CMOS predictive technology model.