A design of silicon based vertical interconnect for 3D MEMS devices under the consideration of thermal stress

3D MEMS 소자에 적합한 열적 응력을 고려한 수직 접속 구조의 설계

  • Jeong, Jin-Woo (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Kim, Hyeon-Cheol (School of Electrical Engineering and Computer Science, Seoul National University) ;
  • Chun, Kuk-Jin (School of Electrical Engineering and Computer Science, Seoul National University)
  • 정진우 (서울대학교 전기컴퓨터공학부) ;
  • 김현철 (서울대학교 전기컴퓨터공학부) ;
  • 전국진 (서울대학교 전기컴퓨터공학부)
  • Published : 2008.02.25

Abstract

Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.

3D MEMS 소자 또는 적층형 패키지에 응용하기 위해서 실리콘 관통 비아를 이용한 새로운 수직 접속 방법을 제안하고 그 실효성을 증명하기 위해 제작하였다. 제안된 실리콘 관통 비아는 기존의 관통 비아에서 도전 물질로 사용되던 구리대신 실리콘을 적용하였다. 그 결과 열팽창 계수 차이에 의한 열응력 줄일 수 있어 높은 온도에서 이루어지는 MEMS 공정과 병행 가능하게 되었다. $30{\mu}m$ 두께의 실리콘 기판 2층이 적층되었으며 $40{\mu}m$$50{\mu}m$의 간격을 가지는 관통 비아 배열을 제작하였다. 관통 비아의 전기적 특성을 측정하고 분석하였다. 측정된 저항 값은 $169.9\Omega$이었다.

Keywords

References

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