ETRI Journal

Electronics and Telecommunications Research Institute (한국전자통신연구원)
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A New Field Programmable Gate Array: Architecture and Implementation

  • Published : 1995.07.31
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Abstract

A new architecture of field programmable gate array for high-speed datapath applications is presented. Its implementation is facilitated by a configurable interconnect technology based on a one-time, two-terminal programmable, very low-impedance anti-fuse and by a configurable logic module optimized for datapath applications. The configurable logic module can effectively implement diverse logic functions including sequential elements such as latches and flip-flops, and arithmetic functions such as one-bit full adder and two-bit comparator. A novel programming architecture is designed for supplying large current through the anti-fuse element, which drops the on-resistance of anti-fuse below $20{\Omega}$. The chip has been fabricated using a $0.8-{\mu}m$ n-well complementary metal oxide semiconductor technology with two layers of metalization.

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References

  1. Field-Programmable Gate Arrays Brown, Stephen D.(et al.)
  2. International Electron Devices Meeting Dielectric based antifuse for logic and memory ICs Esmat Hamdy(et al.)
  3. IEEE 1993 Custom Integrated Circuits Conference Optimized reconfigurable cell array architecture for high-performance field programmable gate arrays Britton, Barry K.(et al.)
  4. IEEE 1990 Custom Integrated Circuits Conference Third-generation architecture boosts speed and density of field-programmable gate arrays Hung-cheng Hsieh(et al.)
  5. IEEE 1989 Custom Integrated Circuits Conference A 5000-gate CMOS EPLD with multiple logic and interconnect arrays Wong, Sau C.(et al.)
  6. IEEE J. of Solid-State Circuits v.24 no.3 An architecture for electrically configurable gate arrays Gamal, Abbas El(et al.)
  7. IEEE Design & Test of Computers An MPGA-like FPGA Marple, David
  8. Electronic Design Compare ASIC capacities with gate array benchmarks Osann, Bob;Gamal, Abbas El
  9. IEEE 1993 Custom Integrated Circuits Conference PREP benchmarks for programmable logic devices McCarty, Dennis;Faria, Donald;Alfka, Peter
  10. Logic synthesis and optimization benchmarks user guide Yang, S.
  11. ACM/SIGDA First International Workshop on Field-Programmable Gate Arrays An improved synthesis algorithm for multiplexor-based PGAs Murgai, R.;Brayton, R.K.;Sangiovanni-Vincentelli, A.