Browse > Article

A design of silicon based vertical interconnect for 3D MEMS devices under the consideration of thermal stress  

Jeong, Jin-Woo (School of Electrical Engineering and Computer Science, Seoul National University)
Kim, Hyeon-Cheol (School of Electrical Engineering and Computer Science, Seoul National University)
Chun, Kuk-Jin (School of Electrical Engineering and Computer Science, Seoul National University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.45, no.2, 2008 , pp. 112-117 More about this Journal
Abstract
Vertical interconnection scheme using novel silicon-through-via for 3D MEMS devices or stacked package is proposed and fabricated to demonstrate its feasibility. The suggested silicon-through-via replaces electroplated copper, which is used as an interconnecting material in conventional through-via, with doped silicon. Adoption of doped silicon instead of metal eliminates thermal-mismatch-induced stress, which can make troubles in high temperature MEMS processes, such as wafer bonding and LP-CVD(low pressure chemical vapor deposition). Two silicon layers of $30{\mu}m$ thickness are stacked on the substrate. The through-via arrays with spacing $40{\mu}m$ and $50{\mu}m$ are fabricated successfully. Electrical characteristics of the through-via are measured and analyzed. The measured resistance of the silicon-through-via is $169.9\Omega$.
Keywords
3D MEMS; through-via; vertical interconnect; stacked package;
Citations & Related Records
연도 인용수 순위
  • Reference
1 Kikuchi, T. Gouji, S. Tai, T. Hayashi, S. Okada, N. Tani, M. Ishikawa, S. Yokoi, S. Enokijima, T. Kawamura, Y. Osugi, Y. Masuda, M. Katsukawa, H. Kobayashi, Y. Morita, "Miniaturized quartz vibratory gyrosensor with hammer-headed arms", Proceedings of the 2004 IEEE International on Frequency Control Symposium and Exposition, pp. 330-333, Montréal, Canada, Aug. 2004
2 K. Tanida, M. Umemoto, Y. Tomita, M. Tago, Y. Nemoto, T. Ando, K. Takahashi, "Ultra- high-density 3D chip stacking technology", Electronic Components and Technology Conference, Proceedings. 53rd, pp. 1084-1089, New Orleans, USA, May 2003
3 Lixia Zhou, Joseph M. Kahn, and Kristofer S. J. Pister, "Scanning micromirrors fabricated by an SOI/SOI wafer-bonding process", Journal of Microelectro Mechanical Systems, Vol. 15, no. 1, pp. 26-32, Feb. 2006
4 Kenji Takahashi, Masataka Hoshino, Hitoshi Yonemura, Manabu Tomisaka, Masahiro Sunohara, Michinobu Tanioka, Tomotoshi Sato, Kazumi Kojima, and Hiroshi Terao, "Development of Advanced 3D Chip Stacking Technology with Ultra-Fine Interconnection", Proceedings of 51st Electronic Components and Technology Conference, pp. 541-546, Orlando, USA, May 2001
5 Jinwoo Jeong, Eunsung Lee, Hyeon Cheol Kim, Changyoul Moon, Kukjin Chun, "Si via interconnection technique for 3D MEMS package", IEEE SENSORS 2006, pp.329, Daegu, Korea, Oct. 2006
6 Silke H. Christiansen, Rajendra Singh, and Ulrich Gösele, "Wafer Direct Bonding: From Advanced Substrate Engineering to Future Applications in Micro/Nano electronics", Proceedings of the IEEE, Vol. 94, issue 12, pp. 2060-2106, Dec. 2006
7 C.-J. Lin, M.-T. Lin, S.-P. Wu and F.-G. Tseng, "High density and through wafer copper interconnections and solder bumps for MEMS wafer-level packaging", Microsystem technologies: sensors, actuators, systems integration, Vol. 10, no. 6/7, pp. 517-521, 2004   DOI   ScienceOn
8 Said F. Al-sarawi, Derek Abbott, and Paul D. Franzon, "A review of 3-D packaging technology", IEEE Transactions on Components, Packaging, and Manufacturing Technology-Part B, Vol. 21, no. 1, pp. 2-14, Feb. 1998   DOI   ScienceOn