• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제24권10호
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• pp.794-798
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• 2011

This paper was carried out design of 1,700 V Base Resistance Thyristor for fabrication. We decided conventional BRT (base resistance thyristor) device and Trench Gate type one for design. we carried out device and process simulation with T-CAD tools. and then, we have extracted optimal device and process parameters for fabrication. we have analysis electrical characteristics after simulations. As results, we obtained 2,000 V breakdown voltage and 3.0 V Vce,sat. At the same time, we carried out field ring simulation for obtaining high voltage.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제30A권8호
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• pp.72-80
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• 1993

We fabricated 0.3um gate length inverse-T gate MOS(ITMOS) and conventional lightly doped drain oxide spacer MOS(LDDMOS), and studied electrical characteristics for comparison. Threshold voltage of 0.3um gate length device was 0.58 V for ITMOS and 0.6V for LDDMOS. Measured subthreshold characteristics showed a slope of 85mV/decades for both ITLDD and LDDMOS. Maximum transconductance at V S1ds T=V S1gs T=3.3V was 180mS/mm for ITMOS and 163mS/mm for LDDMOS respectively. GIDL current was observed to be 0.1pA/um for ITOMS and 0.8pA/um for LDDMOS. Substrate current of ITMOS as a function of drain current was found to be reduced by a foactor of 2.5 compared with that of LDDMOS.

• Journal of the Korean Institute of Telematics and Electronics A
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• 제31A권9호
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• pp.156-163
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• 1994

A new circuit simulator for submicron MOS desings was developed by enhancing SPICE3. The minimum conductance stepping, source stepping and pseudo transient methods are applied to improve the convergence. and SECSPICE uses the variation rate of the node volgage in the timestep algorithm. The modified BSIM model was implemented in SECSPICE for submicron MOS designs. And it gives the powerful user environments such as graphic user environments. As the results of test using real measured device data and circuits used in real production desing, we found it gave more accurage results than BSIM and the execution speed was 1.5~2.8 times faster than SPICE3.

• JSTS:Journal of Semiconductor Technology and Science
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• 제6권1호
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• pp.43-51
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• 2006

80-nm self-aligned n-and p-channel I-MOS devices were demonstrated by using a novel fabrication method featuring double sidewall spacer, elevated drain structure and RTA process. The fabricated devices showed a normal transistor operation with extremely small subthreshold swing less than 12.2 mV/dec at room temperature. The n- and p-channel I-MOS devices had an ON/OFF current of 394.1/0.3 ${\mu}A$ and 355.4/8.9 ${\mu}A$ per ${\mu}m$, respectively. We also investigated some critical issues in device design such as the junction depth of the source extension region and the substrate doping concentration.

• Journal of the Semiconductor & Display Technology
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• 제16권2호
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• pp.49-54
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• 2017

In this paper, recent researches on new and renewable energy have been conducted due to problems such as energy exhaustion and environmental pollution, and new researches on high efficiency and high speed switching are needed. Therefore, we compared the efficiency by using high speed switching devices instead of IGBT which can't be used in high speed switching. The experiment was performed theoretically by applying the same parameters of the high speed switching devices which are the Cool MOS of Infineon Co., SiC C3M of Cree, and GaN FET device of Transform, by implementing the DC-DC boost converter and measuring the actual efficiency for output power and frequency. As a result, the GaN FET showed good efficiency at all switching frequency and output power.

• Journal of the Korea Academia-Industrial cooperation Society
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• 제9권1호
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• pp.47-52
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• 2008

As the packing density of IC devices gets ever higher, the thickness of the gate $SiO_2$ layer of the MOS devices is now required to be reduced down to 1 nm. For such a thin $SiO_2$ layer, the MOS device cannot operate properly because of tunneling current and threshold voltage shift. Hence there has been much effort to develop new dielectric materials which have higher dielectric constants than $SiO_2$ and is free from such undesirable effects. In this work, the physical and electrical characteristics of ALD $ZrO_2$ film have been studied. After deposition of a thin ALD $ZrO_2$ film, it went through thermal treatment in the presence of argon gas at $800^{\circ}C$ for 1 hr. The characteristics of morphology, crystallization kinetics, and interfacial layer of $Pt/ZrO_2/Si$ samples have been investigated by using the analyzing instruments like XRD, TEM and C-V plots. It has been found that the characteristics of the $Pt/ZrO_2/Si$ device was enhanced by the thermal treatment.

• Journal of the Korean Society of Industry Convergence
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• 제5권1호
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• pp.39-43
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• 2002

In present much CMOS devices used in VLSI circuit and Logic circuit. With increasing a number of device in VLSI, the confidence becomes more serious. This paper describe the mechanism of breakdown on CMOS, especially n-MOS, based on Hydro Dynamic model with device self-heating. Additionally, illustrate the CMOS latch-up characteristics on simplified device structure on this paper.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제18권1호
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• pp.17-23
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• 2005

The switching characteristics of MOS-Controlled Thyristor(MCT) is studied with variation of the channel length and impurity concentration in ON and OFF FET channel. The proposed MCT power device has the lateral structure and P-epitaxial layer in substrate. Two dimensional MEDICI simulator and PSPICE simulator are used to study the latch-up current and forward voltage-drop from the characteristics of I-V and the switching characteristics with variation of channel length and impurity concentration in P and N channel. The channel length and N impurity concentration of the proposed MCT power device show the strong affect on the transient characteristics of current and power. The N channel length affects only on the OFF characteristics of power and anode current, while the N doping concentration in P channel affects on the ON and OFF characteristics.

• Journal of information and communication convergence engineering
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• 제5권2호
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• pp.109-111
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• 2007

In this paper, MOS devices with ultrathin gate dielectrics (5.5 nm) are characterized and compared with those with conventional oxides particularly for nanoscale CMOS applications. Nitrogen concentrations and profiles in the nitride gate dielectrics were obtained that will play an important role in improving both hot-carrier lifetime and resistance to boron penetration. This approach seems very useful for future nanoscale CMOS device applications.

• Proceedings of the KIEE Conference
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• 대한전기학회 1989년도 하계종합학술대회 논문집
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• pp.359-363
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• 1989

Recently, it is reported that the behavior of thermal $SiO_2$ under high electric field and current condition has a major effect on MOS device degration. Furthermore, when thin oxide films are applied in practical device, the presence of oxide defects will be a serious problem. In this paper, because TDDB is the useful method to measure the effective density of defects, we stressed MOS structure that is 150 A of thermally grown $SiO_2$as a function of electric field (9-19 MV/cm), temperature ($22^{\circ}C$ - $150^{\circ}C$) and current. By examing TDDB under positive voltage, long-term oxide breakdown reliabiliy is described. From these data, breakdown wearout limitation for the oxide films can be characterized.