• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.195-196
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• 2005

In recent years, as the needs of MOS's a high quality is desired to get the superior electrical characteristics and reliability on MOSFET. As an alternative gate dielectric have drawn considerable alternation due to their superior performance and reliability properties over MOSFET, 2'nd silicidation formation process has been proposed as a dielectric growth/annealing process. In this study the author observed process characteristics on MOS structure. In view points of the process characteristics of MOS capacitor, the oxygen & polysilicon was analyzed by SIMS analysis on l'st & 2'nd Ti process, the oxygen and Si2 contents[Count/sec] of 1.5e3 & 3.75e4 on l'st process and l.1e3 & 2.94e4 on 2'nd process, the Ti contents' of 8.2e18 & 6.5e18 on 1'st and 2'nd process. The sheet resistance[$\Omega/sq.$] was 4.5 & 4.0, the film stress[dyne/cm 2] of 1.09e10 & 1.075e10 on l'st and 2'nd process. I could achieved the superior MOS characteristics by 2'nd silicidation process.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.612-615
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• 2004

A high-voltage generator is used to program the anti-fuse of the semiconductor chip. A new high-voltage generator consists of PN diodes and new stack type capacitors. An oscillator supply pulses to the high-voltage generator. The pulse period of the oscillator is delayed by controlling gate-voltage of the MOS. The pulse period is about 27ns, therefore the pulse frequency is about 37MHz. The threshold voltage of PN diode is about 0.8V. The capacitance of new stack type capacitor is about 4pF. The output voltage of the new high-voltage generator is about 7.9V and its current capacity is about $488{\mu}$A.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.1
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• pp.21-26
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• 2004

Ultra-thin silicon dioxides were grown on p-type(100) oriented silicon employing rapid thermal dry oxidation technique at the temperature range of 850∼1050 $^{\circ}C$. The growth rate of the ultra-thin film was fitted well with tile model which was proposed recently by da Silva ＆ Stosic. The capacitance-voltage, current-voltage, characteristics were used to study the electrical properties of these thin oxides. The minimum interface state density around the midgap of the MOS capacitor having oxide thickness of 111.6 $\AA$ derived from the C-V curve was ranged from 6 to 10${\times}$10$^{10}$ /$\textrm{cm}^2$eV.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.100-106
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• 2010

The impact of surface quantization on device parameters of a Si metal oxide semiconductor (MOS) capacitor has been analyzed in the present work. Variation of conduction band bending, position of discrete energy states, variation of surface potential, and the variation of inversion carrier concentration at charge centroid have been analyzed for different gate voltages, substrate doping concentrations and oxide thicknesses. Oxide thickness calculated from the experimental C-V data of a MOS capacitor is different from the actual oxide thickness, since such data include the effect of surface quantization. A correction factor has been developed considering the effect of charge centroid in presence of surface quantization at strong inversion and it has been observed that the correction due to surface quantization is crucial for highly doped substrate with thinner gate oxide.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.7
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• pp.557-562
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• 2000

160nm thick amorphous Si and polycrystalline Si were each deposited on to 10nm thick SiO$_2$, Co monolayer and Co/Ti bilayer were sequentially evaporated to form Co-polycide. Then MOS capacitors were fabricated by BF$_2$ ion-implantation. The characteristics of the fabricated capacitor samples depending upon the drive-in annel conductions were measured to study the effects of thermal stability of CoSi$_2$and dopant redistribution on electrical properties of Co-polycide gates. Results for capacitors using Co/Ti bilayer and drive-in annealed at 80$0^{\circ}C$ for 20~40sec. showed excellent C-V characteristics of gate electrode.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.10a
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• pp.293-294
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• 2014

본 논문에서는 MOS 커패시터를 이용하여 12비트 1MSps 연속 근사화 레지스터 아날로그-디지털 변환기(Successive Approximation Register Analog-to-Digital Converter, SAR ADC)를 설계하였다. 설계된 아날로그-디지털 변환기는 매그나칩/SK하이닉스 $0.18{\mu}m$ 공정을 이용하였으며, Cadence Tool을 이용하여 시뮬레이션 및 레이아웃을 하였다. 시뮬레이션 결과 1.8V의 공급전압에서 전력 소모는 3.22mW였고, 유효 비트수는 11.5bit의 결과를 보였다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.699-705
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• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.358-358
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• 2014

인간과 기기간의 상호작용 심화에 의하여 모든 기기의 지능화, 첨단화 등이 요구됨에 따라 정보 기술 및 디스플레이 기술의 개발이 활발히 이루어지고 있는 가운데 투명 전자 소자에 대한 연구가 급증하고 있다. 산화물 반도체는 가시광 영역에서 투명하고, 비정질 반도체에 비하여 이동도가 100 배 이상 크고, 결정화 공정을 거친 폴리 실리콘과 비슷한 값을 가지거나 조금 낮으며 유연한 소자에도 쉽게 적용이 가능하다는 장점을 가지고 있어 투명 전자 소자 제작시에 주로 이용되는 물질이다. 대부분의 산화물 반도체 박막 증착 방법은 스퍼터링 방법이나 유기금속 화학증착법과 같은 방법으로 막을 형성하는데 이러한 증착 방법들은 고품질의 박막을 성장시킬 수 있다는 장점이 있으나 고가의 진공장비 및 부대 시설이 이용되고 이로 인한 제조비용의 상승이 되고, 기판 선택에 제약이 있는 단점이 있다. 따라서, 이러한 문제점을 개선하기 위하여 고가의 진공 장비가 필요 없이 스핀 코팅 방법이나 딥핑 방법 등에 의하여 공정 단계의 간소화, 높은 균일성, 기판 종류에 상관없는 소자의 대면적화가 가능한 용액 공정 기술이 각광을 받고 있다. 그러나 용액 공정 기반의 박막을 형성하기 위해서는 비교적 높은 공정온도 혹은 압력 등의 외부 에너지를 필요로 하므로 열에 약한 유리 기판이나 유연한 기판에 적용하기가 어렵다. 최근 이러한 문제점을 해결하기 위하여 높은 온도의 열처리(thermal annealing) 를 대신 할 수 있는 microwave irradiation (MWI)에 대한 연구가 보고되고 있다. MWI는 $100^{\circ}C$ 이하에서의 저온 공정이 가능하여 높은 공정 온도에 대한 문제점을 해결할 뿐만 아니라 열처리 방향을 선택적으로 할 수 있다는 장점을 가지고 있어 현재 투명 디스플레이 분야에서 주로 이용되고 있다. 따라서 본 연구에서는 HfOx 기반의 metal-oxide-semiconductor (MOS) capacitor를 제작하여 MWI에 따른 전기적 특성을 평가하였다. MWI는 금속의 증착 전과 후, 그리고 시간에 따른 조건을 적용하였으며 최적화된 조건의 MWI은 일반적인 퍼니스 장비에서의 높은 온도 열처리에 준하는 우수한 전기적 특성을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.265-270
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• 2017

4H-SiC has attracted attention for high-power and high-temperature metal-oxide-semiconductor field-effect transistors (MOSFETs) for industrial and automotive applications. The gate oxide in the 4H-SiC MOS system is important for switching operations. Above $1000^{\circ}C$, thermal oxidation initiates $SiO_2$ layer formation on SiC; this is one advantage of 4H-SiC compared with other wide band-gap materials. However, if post-deposition annealing is not applied, thermally grown $SiO_2$ on 4H-SiC is limited by high oxide charges due to carbon clusters at the $SiC/SiO_2$ interface and near-interface states in $SiO_2$; this can be resolved via low-temperature deposition. In this study, low-temperature $SiO_2$ deposition on a Si substrate was optimized for $SiO_2/4H-SiC$ MOS capacitor fabrication; oxide formation proceeded without the need for post-deposition annealing. The $SiO_2/4H-SiC$ MOS capacitor samples demonstrated stable capacitance-voltage (C-V) characteristics, low voltage hysteresis, and a high breakdown field. Optimization of the treatment process is expected to further decrease the effective oxide charge density.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.83-90
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• 1998

The effects of dopant activation anneal on GOI (Gate Oxide Integrity) of MOS capacitor with amorphous silicon gate electrode were investigated. It was found that the amorphous silicon gate electrode was crystallized and the dopant atoms were sufficiently activated by activation anneal. The mechanical stress of gate electrode that reveals large compressive stress in amorphous state, was released with increase of anneal temperature from $700^{\circ}C$ to 90$0^{\circ}C$. The resistivity of gate electrode polycrystalline silicon film is decreased by the increase of anneal temperature. The reliability of thin gate oxide and interface properties between oxide and silicon substrate greatly depends on the activation anneal temperature. The charge trapping characteristics as well as oxide reliability are improved by the anneal of 90$0^{\circ}C$ compare to that of $700^{\circ}C$ or 80$0^{\circ}C$. Especially, the lifetimes of the thin gate oxide estimated by TDDB method is 3$\times$10$^{10}$ for the case of $700^{\circ}C$ anneal, is significantly increased to 2$\times$10$^{12}$ for the case of 90$0^{\circ}C$ anneal. Finally, the interface trap density is reduced with relaxation of mechanical stress of gate electrode.