• Environmental Engineering Research
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• 제21권4호
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• pp.409-419
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• 2016

As a major energy consumption province, the issue about the carbon emissions in Hebei Province, China has been concerned by the government. The carbon emissions can be effectively reduced due to a more rational energy consumption structure. Thus, in this paper the constraint of low carbon emissions is considered as a foundation and four energies--coal, petroleum, natural gas and electricity including wind power, nuclear power and hydro-power etc are selected as the main analysis objects of the adjustment of energy structure. This paper takes energy cost minimum and carbon trading cost minimum as the objective functions based on the economic growth, energy saving and emission reduction targets and constructs an optimization model of energy consumption structure. And empirical research about energy consumption structure optimization in 2015 and 2020 is carried out based on the energy consumption data in Hebei Province, China during the period 1995-2013, which indicates that the energy consumption in Hebei dominated by coal cannot be replaced in the next seven years, from 2014 to 2020, when the coal consumption proportion is still up to 85.93%. Finally, the corresponding policy suggestions are put forward, according to the results of the energy structure optimization in Hebei Province.

• 센서학회지
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• 제27권1호
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• pp.59-63
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• 2018

Among Internet of things (IoT) applications, the most demanding requirements for the widespread realization of many IoT visions are security and low power. In terms of security, IoT applications include tasks that are rarely addressed before such as secure computation, trusted sensing, and communication, privacy, and so on. These tasks ask for new and better techniques for the protection of data, software, and hardware. An integral part of hardware cryptographic primitives are secret keys and unique IDs. Physical Unclonable Functions(PUF) are a unique class of circuits that leverage the inherent variations in manufacturing process to create unique, unclonable IDs and secret keys. In this paper, we propose a low power Arbiter PUF circuit with low error rate and high reliability compared with conventional arbiter PUFs. The proposed PUF utilizes a power gating structure to save the power consumption in sleep mode, and uses a razor flip-flop to increase reliability. PUF has been designed and implemented using a FPGA and a ASIC chip (a 0.35 um technology). Experimental results show that our proposed PUF solves the metastability problem and reduce the power consumption of PUF compared to the conventional Arbiter PUF. It is expected that the proposed PUF can be used in systems required low power consumption and high reliability such as low power encryption processors and low power biomedical systems.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2004년도 Asia Display / IMID 04
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• pp.159-163
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• 2004

We have introduced fourth generation PDPs last year. The performance of these PDPs is the highest level among TV displays. At the same time the power consumption of them has reached to the lowest level among FPDs (Flat Panel Displays). High panel luminous efficacy and low address power are necessary for the reduction of total power consumption. Following technologies have been developed and applied to the fourth generation PDPs. High panel luminous efficacy: T-shape electrode, waffle rib structure, high Xe content gas Low address power; CLEAR driving method, etc.

• 정보처리학회논문지A
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• 제14A권3호
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• pp.147-150
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• 2007

본 논문에서는 작은 점유면적과 저 전력 소모 특성을 갖도록 CPL(Complementary Pass-Transistor Logic) 논리구조의 전가산기에 저 전압 스윙 기술을 적용하여 16$\times$16 비트 병렬 곱셈기를 설계하였다. 회로구성상 CPL 논리구조는 CMOS 논리구조에 비해 NMOS 트랜지스터만을 사용하기 때문에 작은 면적을 소비한다. 저 전압 스윙 기술은 회로에 공급되는 전압보다 낮은 전압 레벨에서 출력 동작을 하여 전력 소모를 감소시키는 기술이다. 본 논문에서는 전가산기의 출력 단에 사용되는 인버터에 저 전압 스윙 기술을 적용하여 저 전력 소모 특성을 갖는 16$\times$16 비트 병렬 곱셈기를 설계하였다 설계한 회로는 17.3%의 전력 소모 감소와 16.5%의 전력소모와 지연시간의 곱(Power Delay) 감소가 이루어졌다.

• 디지털산업정보학회논문지
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• 제10권1호
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• pp.1-6
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• 2014

In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating a problem occurs when the node being split to overcome the area and power consumption can reduce the algorithm. CPLD to configure and limitations of the LE is that the number of OR-terms. FC consists of an OR node is divided into mainly as a way to reduce the power consumption with the highest number of output nodes is divided into a top priority. The highest number of output nodes with the highest number of switching nodes become a cut-point. Division of the node is the number of OR-terms of the number of OR-terms LE is greater than adding the input and output of the inverter converts the AND. Reduce the level, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmark experimental results of 13% compared to the number of logical blocks decreased. 8% of the power consumption results in a reduced efficiency of the algorithm represented been demonstrated.

• 디지털콘텐츠학회 논문지
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• 제14권1호
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• pp.1-5
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• 2013

본 논문은 효율적인 CPLD 저전력 알고리즘을 제안하였다. 제안한 알고리즘은 DAG를 이용한 그래프 분할 방식을 적용하였다. 주어진 회로를 DAG로 표현한 후 각각의 노드의 값을 설정하여 회로를 구현하고자 하는 CPLD의 구성 요소에 맞도록 매핑 가능 클러스터를 생성한다. 생성된 매핑 가능 클러스터의 OR 텀수와 입력 변수의, 출력 변수의 수를 고려하여 매핑 가능 클러스터의 소모 전력 값을 구한다. 생성된 매핑 가능 클러스터와 소모 전력 값을 고려하여 소모전력이 최소가 되는 매핑 가능 클러스터를 선정하여 회로를 구현한다. 실험은 [9]와 비교하였으며, 소모전력이 감소되어 알고리즘의 효율성이 입증되었다. 논문에서는 소모 전력을 위한 FPGA 알고리즘을 제안하였다.

• 대한전자공학회논문지SD
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• 제43권10호
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• pp.134-139
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• 2006

본 논문은 버스의 소비 전력을 비용 함수로 정의하여 버스의 소비 전력을 줄이는 버스 기반 평면계획을 제안한다. 기존 버스 기반 평면계획의 비용함수는 버스의 면적만을 줄이고 버스의 소비전력은 고려하지 않았다. 그러나 버스의 분할 설계 방식을 가정한 경우 버스의 소비 전력이 면적에 반드시 비례하지는 않기 때문에 기정의 비용함수로는 버스의 소비 전력을 반영할 수가 없다. 본 논문에서는 버스 분할 설계 기법이 적용된 경우를 가정하고 버스에 연결된 블록간의 통신량과 실제 거리를 고려하여 버스의 소비 전력을 비용함수에 추가하였다. 실험 결과 새로운 비용함수를 사용한 버스 기반 평면계획에서는 버스의 소비 전력에 관련된 값이 평균 11.43%만큼 감소하였다.

• 센서학회지
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• 제29권1호
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• pp.68-73
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• 2020

This paper proposes an asynchronous circuit design methodology using a new Single Gate Sleep Convention Logic (SG-SCL) with advantages such as low area overhead, low power consumption compared with the conventional null convention logic (NCL) methodologies. The delay-insensitive NCL asynchronous circuits consist of dual-rail structures using {DATA0, DATA1, NULL} encoding which carry a significant area overhead by comparison with single-rail structures. The area overhead can lead to high power consumption. In this paper, the proposed single gate SCL deploys a power gating structure for a new {DATA, SLEEP} encoding to achieve low area overhead and low power consumption maintaining high performance during DATA cycle. In this paper, the proposed methodology has been evaluated by a liquid state machine (LSM) for pattern and digit recognition using FPGA and a 0.18 ㎛ CMOS technology with a supply voltage of 1.8 V. the LSM is a neural network (NN) algorithm similar to a spiking neural network (SNN). The experimental results show that the proposed SG-SCL LSM reduced power consumption by 10% compared to the conventional LSM.

• ETRI Journal
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• 제34권5호
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• pp.727-733
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• 2012

This paper demonstrates a new driving scheme that allows reducing the supply voltage of data drivers for low-power active matrix organic light-emitting diode (AMOLED) displays. The proposed technique drives down the data voltage range by 50%, which subsequently diminishes in the peak power consumption of data drivers at the full white pattern by 75%. Because the gate voltage of a driving thin film transistor covers the same range as a conventional driving scheme by means of a level-shifting scheme, the low-data supply scheme achieves the equivalent dynamic range of OLED currents. The average power consumption of data drivers is reduced by 60% over 24 test images, and power consumption is kept below 25%.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.545-546
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• 2008

This paper presents a low power CMOS low noise amplifier for UWB applications. To reduce the power consumption, two cascode amplifiers was stacked in DC. Designed with $0.18-{\mu}m$ CMOS technology, the proposed LNA achieves 20dB flat gain, below 3dB noise figure, and the power consumption of 5.2mW from a 1.8 V supply voltage.