Journal of Korea Society of Digital Industry and Information Management (디지털산업정보학회논문지)

Korea Society of Digital Industry and Information Management (디지털산업정보학회)
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A CPLD Low Power Algorithm considering the Structure

구조를 고려한 CPLD 저전력 알고리즘

  • 김재진 (강동대학교 신재생에너지과)
  • Received : 2014.02.10
  • Accepted : 2014.02.21
  • Published : 2014.03.30
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Abstract

In this paper, we propose a CPLD low power algorithm considering the structure. The proposed algorithm is implemented CPLD circuit FC(Feasible Cluster) for generating a problem occurs when the node being split to overcome the area and power consumption can reduce the algorithm. CPLD to configure and limitations of the LE is that the number of OR-terms. FC consists of an OR node is divided into mainly as a way to reduce the power consumption with the highest number of output nodes is divided into a top priority. The highest number of output nodes with the highest number of switching nodes become a cut-point. Division of the node is the number of OR-terms of the number of OR-terms LE is greater than adding the input and output of the inverter converts the AND. Reduce the level, power consumption and area. The proposed algorithm to MCNC logic circuits by applying a synthetic benchmark experimental results of 13% compared to the number of logical blocks decreased. 8% of the power consumption results in a reduced efficiency of the algorithm represented been demonstrated.

Keywords

References

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