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http://dx.doi.org/10.3745/KIPSTA.2007.14-A.3.147

Design of a Low-Power Parallel Multiplier Using Low-Swing Technique  

Kim, Jeong-Beom (강원대학교 전기전자공학부)
Publication Information
The KIPS Transactions:PartA / v.14A, no.3, 2007 , pp. 147-150 More about this Journal
Abstract
This paper describes a new low-swing inverter for low power consumption. To reduce a power consumption, an output voltage swing is in the range from 0 to VDD-2VTH. This can be done by the inverter structure that allow a full swing or a swing on its input terminal without leakage current. Using this low-swing voltage technology, we proposed a low-power 16$\times$16 bit parallel multiplier. The proposed circuits are designed with Samsung 0.35$\mu$m standard CMOS process at a 3.3V supply voltage. The validity and effectiveness are verified through the HSPICE simulation.. Compared to the previous works, this circuit can reduce the power consumption rate of 17.3% and the power-delay product of 16.5%.
Keywords
Low-Power Circuit Design; Low-Swing Technology; CPL;
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