• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.9 no.3
• /
• pp.582-586
• /
• 2005

This paper presents a new structure of Phase Locked Loop(PLL) which changes its loop bandwidth according to the locking status. The proposed PLL consists of a conventional PLL and, Locking Status Indicator(LSI). The LSI decides the operating bandwidth of loop filler. When the PLL becomes out of lock, the PLL increases the loop bandwidth and achieves fast locking. When the PLL becomes in-lock, this PLL decreases the loop bandwidth and minimizes phase noise output. The PLL can achieve fast locking and low phase noise output at the same time. Proposed PLL's locking time is less than $40{\mu}s$ and spur is 76.1dBc. It is simulated by HSPICE in a Hynix CMOS $0.35{\mu}m$ Process.

• Journal of information and communication convergence engineering
• /
• v.3 no.3
• /
• pp.142-145
• /
• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2017.05a
• /
• pp.691-693
• /
• 2017

A novel structure of fast locking phase locked loop (PLL) with time difference detector and Lock status indicator (LSI) is proposed in this paper. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.21 no.2
• /
• pp.339-344
• /
• 2017

A novel structure of phase locked loop (PLL) which has small size and fast locking time with Early-late detector, Duty-rate modulator, and Lock status indicator (LSI) is proposed in this paper. The area of loop filter usually occupying the larger portion of the chip is minimized using a single small capacitor. While the conventional PLL with a single capacitor loop filter cannot work stably, the proposed PLL with two charge pumps works stably because the output voltage waveform of the proposed a single capacitor loop filter is the same as the output voltage waveform of the conventional 2nd-order loop filter. The two charge pumps are controlled by the Early-late detector which detects early-late status of UP and DN signals, and Duty-rate modulator which generates a steady duty-rate signal. Fast locking time is achieved using LSI. It has been simulated and proved by HSPICE in a CMOS $0.18{\mu}m$ 1.8V process.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.2
• /
• pp.71-77
• /
• 2009

A novel phase-locked loop(PLL) architecture with multiple charge pumps for fast locking has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. The fast locking PLL that changes its loop bandwidth through controlling charge pumps depending on locking status has been designed. The capacitor usually occupying the larger portion of the chip is also minimized with the proposed scheme. Therefore, the PLL size of $990{\mu}m\;{\times}\;670{\mu}m$ including resistors and capacitors at the bandwidth of 29.9KHz has been achieved. It has been fabricated with 3.3V $0.35{\mu}m$ CMOS process. The locking time is less than $6{\mu}s$ with the measured phase noise of -90.45dBc/Hz @1MHz at 851.2MHz output frequency.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.22 no.8
• /
• pp.1068-1075
• /
• 2018

In this paper, a novel PLL has been proposed that reduces the size of the loop filter while suppressing spur by using a VCO with two inputs. Through the stability analysis according to the operating status, the PLL is designed to operate stably after the phase fixing. The capacitor of loop filter usually occupies larger area of PLL. It is a VCO that can reduce the size of the loop filter by increasing the effective capacitance of the capacitor through the simultaneous charge and discharge operation by two charge pumps and has two signals operating in opposite phases. The settling time of set to $80{\mu}s$ approximately by using a LSI(Locking Status Indicator) indicating the phase locking status. The proposed PLL is designed using a supply voltage of 1.8V and a $0.18{\mu}m$ CMOS process.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.46 no.4
• /
• pp.37-44
• /
• 2009

A novel phase-locked loop(PLL) architecture with resistance and capacitance scaling scheme has been proposed. The proposed PLL has three charge pumps. The effective capacitance and resistance of the loop filter can be scaled up/down according to the locking status by controlling the direction and magnitude of each charge pump current. This architecture makes it possible to have a narrow bandwidth and low resistance in the loop filter, which improves phase noise and reference spur characteristics. It has been fabricated with a 3.3V $0.35{\mu}m$ CMOS process. The measured locking time is $25{\mu}s$ with the measured phase noise of -105.37 dBc/Hz @1MHz and the reference spur of -50dBc at 851.2MHz output frequency

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.4
• /
• pp.819-825
• /
• 2016

In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.

• Clinics in Shoulder and Elbow
• /
• v.19 no.4
• /
• pp.216-222
• /
• 2016

Background: We investigated the effectiveness of fibular strut allograft augmentation of proximal humerus fractures to prevent varus deformity in patients over the age of 65 years with insufficient medial support. Methods: We analyzed the clinical and radiological outcomes of locking plate fixation with adjunct fibular strut allograft augmentation in 21 patients with proximal humeral fractures. The inclusion criteria were age (65-year-old or older); presence of severe medial comminution; inadequate medial support; and those who could participate in at least a one year follow-up. The average age was 76.4 years. We analyzed each patient's Constant score, our indicator of clinical outcome. As radiological parameters, we analyzed time-to-bone union; restoration of the medial hinge; difference between the immediately postoperative and the last follow-up humeral neck-shaft angles;; and anatomical reduction status, which was assessed using the Paavolainen method. Results: A successful bone union was achieved in all patients at an average of 11.4 weeks. We found that the average Constant score was 74.2, showing a satisfactory outcome. The average difference in the humeral neck-shaft angles between the immediately postoperative time-point and at the final follow-up was $3.09^{\circ}$. According to the Paavolainen method, the anatomical reduction was rated excellent. The medial hinge was restored in 14 of 21 patients. Although we did not find evidence for osteonecrosis, we found that a single patient had a postoperative complication of screw cut-out. Conclusions: Fibular strut allografting as an adjunct treatment of proximal humeral fractures may reduce varus deformity in patients with severe medial comminution.