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http://dx.doi.org/10.6109/jkiice.2016.20.4.819

Design of Dual loop PLL with low noise characteristic  

Choi, Young-Shig (Department of Electronic Engineering, Pukyong National University)
Ahn, Sung-Jin (Department of Electronic Engineering, Pukyong National University)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.20, no.4, 2016 , pp. 819-825 More about this Journal
Abstract
In this paper, a phase locked loop structure with parallel dual loop which have a different bandwidth has been proposed. The bandwidths depending on transfer functions are obtained through dual loops. Two different bandwidths of each loop are used to suppress noise on the operating frequency range. The proposed phase locked loop has two different voltage controlled oscillator gains to control two different wide and narrow loop filters. Furthermore, it has the locking status indicator to achieve an accurate locking condition. The phase margin of $58.2^{\circ}$ for wide loop and $49.4^{\circ}$ for narrow loop is designed for stable operation and the phase margin of $45^{\circ}$ is maintained during both loops work together. It has been designed with a 1.8V 0.18um complementary metal oxide semiconductor (CMOS) process. The simulation results show that the proposed phase locked loop works stably and generates a target frequency.
Keywords
PLL; Continuous Band-selection; Two Negative Feedback Loops; Phase Noise;
Citations & Related Records
Times Cited By KSCI : 2  (Citation Analysis)
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