• 한국전기전자재료학회논문지
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• 제27권11호
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• pp.686-689
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• 2014

Electrostatic discharge has been considered as a major reliability problem in the semiconductor industry. ESD reliability is an important issue for these products. Therefore, each I/O (Input/Output) PAD must be designed with a protection circuitry that creates a low impedance discharge path for ESD current. This paper presents a novel Lateral Insulated Gate Bipolar (LIGBT)-based ESD protection circuit with latch-up immunity and high robustness. The proposed circuit is fabricated by using 0.18 um BCD (bipolar-CMOS-DMOS) process. Also, TLP (transmission line pulse) I-V characteristic of proposed circuit is measured. In the result, the proposed ESD protection circuit has latch-up immunity and high robustness. These characteristics permit the proposed circuit to apply to power clamp circuit. Consequently, the proposed LIGBT-based ESD protection circuit with a latch-up immune characteristic can be applied to analog integrated circuits.

• 전기학회논문지
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• 제59권11호
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• pp.2089-2092
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• 2010

There are many cases that interrupt the production process because of malfunctions caused by electronic circuit boards which control equipment, but it is difficult to distinctly identify the causes in many cases. Especially, CMOS devices with the control logic circuit return automatically to normal state after their own faults. Therefore it is not easy to analyze the problems with electronic circuit boards. Recently, nuclear power plant experienced a failure due to the malfunction of electronic circuit boards and it was identified that the reason of the malfunction was because of latch-up phenomenon caused by external surge in electronic devices. This paper presents the causes and the phenomenon of latch-up by experiment and also a way using counter EMF diodes, noise filters and surge protective devices to prevent latch-up phenomenon from electronic circuit boards, finally confirms the effectiveness of the result by experiment.

• 대한기계학회논문집A
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• 제38권11호
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• pp.1215-1220
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• 2014

회로차단기에서 가장 중요한 성능은 전기시스템의 이상전류를 신속하게 차단하는 것이다. 이러한 차단시간은 조작기구의 동적 특성에 의한 영향을 받는다. 따라서 회로차단기의 차단시간 단축을 위해서는 조작기구의 최적화가 이루어져야 한다. 본 논문의 가스회로차단기의 조작기는 스프링으로 구동되며 여러 개의 Latch 로 구성되어있다. Latch 들의 상대적 위치와 길이로 정의된 각 설계변수의 차단시간에 대한 영향을 분석하고 이 결과를 통해 설계변수를 선정하여 ADAMS 와 VisualDOC 의 연동을 통해 최적화를 수행하였다. Latch 들의 최적화를 통해 약 22.5% 개극시간을 향상을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권1호
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• pp.58-64
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• 2013

In this paper, two new flip-flop circuits with PCRAM latches that are FF-1 and FF-2, respectively, are proposed not to waste leakage during sleep time. Unlike the FF-1 circuit that has a normal PCRAM latch, the FF-2 circuit has a selective write latch that can reduce the switching activity in writing operation to save switching power at sleep-in moment. Moreover, a sequential sleep-in control is proposed to reduce the rush current peak that is observed at the sleep-in moment. From the simulation of storing '000000' to the PCRAM latch, we could verify that the proposed FF-1 and FF-2 consume smaller power than the conventional 45-nm FF if the sleep time is longer than $465{\mu}s$ and $95{\mu}s$, respectively, at $125^{\circ}C$. For the rush current peak, the sequential sleep-in control could reduce the current peak as much as 77%.

• 대한기계학회논문집A
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• 제38권1호
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• pp.25-30
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• 2014

가스회로차단기의 거동특성은 스프링 래치 시스템을 가진 고속 작동메커니즘에 좌우된다. 고속회로차단기의 차단시간을 줄이기 위해서 연구가 많이 이루어지고 있다. 본 연구에서는 고속회로차단기의 차단시간을 단축하기 위하여 래치의 윤곽최적설계에 관한 연구가 수행된다. 회로차단기의 거동특성을 분석하기 위해서 상용 다물체 동역학 해석프로그램인 MSC/ADAMS 를 이용하였으며, 시뮬레이션 결과는 시험을 통하여 매칭하였다. VisualDOC 를 도입하여 래치의 최적윤곽을 구하였다. 최적설계 수행결과 가스회로차단기의 차단시간을 약 8.6% 개선하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1181-1184
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• 2003

This paper proposes a new Sense Amplifier for MRAM. Current Sense Amplifier employs a latch-type circuit to amplify a signal from the selected memory cell. The proposed Sense Amplifier simplifies the circuit by amplifying the signal using cross-coupled PMOS transistors. It shows the same operation speed as the latch-type Sense Amplifier in simulation and occupies only 85% of the area taken by the latch-type Sense Amplifier.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1998년도 추계종합학술대회 논문집
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• pp.779-782
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• 1998

This paper describes a high-speed Dual-modulus Prescaler (DMP) for RF mobile communication systems with pulse remover using selective latch technique. This circuit achieves high speed and low power consumption by reducing full speed flip-flops and using a selective latch. The proposed DMP consists of only one full speed flip-flop, a selective latch, conventional flip-flops, and a control gate. In order to ensure the timing of control signal, duty cycle problem and propagation delay must be considered. The failling edgetriggered flip-flops alleviate the duty cycle problem andthis paper shows that the propagation delay of control signal doesn't matter. The maximum operating frequency of the proposed DMP with 0.6um CMOS technology is up to 2.2㎓ at 3.3V power supply and the circuit consumes 5.24mA.

• 전기학회논문지
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• 제61권3호
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• pp.422-426
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• 2012

Transient radiation is emitted during a nuclear explosion. Transient radiation causes a fatal error in the CMOS circuit as a Upset and Latch-up. In this paper, transient radiation NMOS, PMOS, INVERTER SPICE model was proposed on the basisi of transient radiation effects analysis using TCAD(Technology Computer Aided Design). Photocurrent generated from the MOSFET internal PN junction was expressed to the current source and Latch-up phenomenon in the INVERTER was expressed to parasitic thyristor for the transient radiation SPICE model. For example, the proposed transient radiation SPICE model was applied to CMOS NAND circuit. SPICE simulated characteristics were similar to the TCAD simulation results. Simulation time was reduced to 120 times compared to TCAD simulation.

• 전자공학회논문지
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• 제50권8호
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• pp.121-127
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• 2013

SRAM, DRAM을 포함한 Memory 소자들은 우주환경에서 고에너지 입자에 취약하다. SEE(Single Event Effect) 또는 TID(Total Ionizing Dose)에 의해서 소자의 비정상적인 동작이 야기될 수 있다. 본 논문은 SRAM의 기본 단위 셀인 Latch 회로를 이용하여 양성자에 대한 취약성을 나타내는 SEU cross section을 추정할 수 있는 방법에 대해서 설명한다. 또한 양성자에 의한 SEU 효과를 줄일 수 있는 Latch 회로를 제안하였다. 두 소자를 이용하여 50b shift register를 $0.35{\mu}m$공정에서 제작하였고, 한국 원자력 의학원의 43MeV 양성자 빔을 이용하여 방사선 조사 실험을 진행하였다. 실험 결과로부터 conventional latch를 이용한 shift register에 비해서 제안한 latch를 이용한 shift register가 방사선 환경에서 내구성이 강한 동작 특성을 가진 다는 것을 확인하였다.

• 전기학회논문지
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• 제67권6호
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• pp.745-752
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• 2018

ICs(Integrated circuits) for nuclear power plant exposed to radiation environment occur malfunctions and data errors by the TID(Total ionizing dose) effects among radiation-damage phenomenons. In order to protect ICs from the TID effects, this paper proposes a radiation-hardening of the logic circuit(D-latch) which used for the data synchronization and the clock division in the ICs design. The radiation-hardening technology in the logic device(NAND) that constitutes the proposed RH(Radiation-hardened) D-latch is structurally more advantageous than the conventional technologies in that it keeps the device characteristics of the commercial process. Because of this, the unit cell based design of the RH logic device is possible, which makes it easier to design RH ICs, including digital logic circuits, and reduce the time and cost required in RH circuit design. In this paper, we design and modeling the structure of RH D-latch based on commercial $0.35{\mu}m$ CMOS process using Silvaco's TCAD 3D tool. As a result of verifying the radiation characteristics by applying the radiation-damage M&S (Modeling&Simulation) technique, we have confirmed the radiation-damage of the standard D-latch and the RH performance of the proposed D-latch by the TID effects.