• Journal of electromagnetic engineering and science
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• v.9 no.1
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• pp.7-11
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• 2009

An Ultra-WideBand(UWB) Low-Noise Amplifier(LNA) is proposed and is implemented in a $0.18-{\mu}m$ CMOS technology. The proposed UWB LNA provides excellent wideband characteristics by combining a High-Pass Filter (HPF) with a conventional resistive-loaded LNA topology. In the proposed UWB LNA, the bell-shaped gain curve of the overall amplifier is much less dependent on the frequency response of the HPF embedded in the input stage. In addition, the adoption of fewer on-chip inductors in the input matching network permits a lower noise figure and a smaller chip area. Measurement results show a power gain of + 10 dB and an input return loss of more than - 9 dB over 2.7 to 6.2 GHz, a noise figure of 3.1 dB at 3.6 GHz and 7.8 dB at 6.2 GHz, an input PldB of - 12 dBm, and an IIP3 of - 0.2 dBm, while dissipating only 4.6 mA from a 1.8-V supply.

• Journal of IKEEE
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• v.19 no.3
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• pp.440-446
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• 2015

This study has examined susceptibility of LNA(Low Noise Amplifier) due to Front-Door Coupling under Narrow-Band high power electromagnetic wave. M/DFR(Malfunction/Destruction Failure Rate) was measured to investigate the diagnostic of IC test. In addition, decapsulation analysis was used to understand the inside of the chip state in LNA devices. The experiments is employed as an open-ended waveguide to study the destruction effects of LNA using a 2.45 GHz Magnetron as a high power electromagnetic wave. The susceptibility level of LNA was assessed by electric field strength, and its failure modes were observed. The malfunction of LNA device has showed as the type of self-reset and power-reset. The electric field strength of malfunction threshold is 524 V/m and 1150 V/m respectively. Also, he electric field of destruction threshold is 1530 V/m. Three types of damaged LNA were observed by decapsulation analysis: component, onchipwire, and bondwire destruction. Based on these results, the susceptibility of the LNA can be applied to a database to help elucidate the effects of microwaves on electronic equipment.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.4
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• pp.283-288
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• 2008

A post-linearization technique for the differrential CMOS LNA is presented. The proposed method uses an additional cross-coupled common-source FET pair to cancel out the third-order intermodulation ($IM_3$) current of the main differential amplifier. This technique is applied to enhance the linearity of CMOS LNA using $0.18-{\mu}m$ technology. The LNA achieved +10.2 dBm IIP3 with 13.7 dB gain and 1.68 dB NF at 2 GHz consuming 11.8 mA from a 1.8-V supply. It shows IIP3 improvement by 6.6 dB over the conventional cascode LNA without the linearizing circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.10
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• pp.33-37
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• 2007

This paper presents the implementation technique to reduce circuit area occupation in designing Low Noise Amplifier (LNA) using vertical shunt symmetric inductor. We applied a vertical shunt symmetric inductor to match the input and output in 3 GHz CMOS LNA to reduce the circuit area. This size efficient amplifier has been designed in a $0.18\;{\mu}m$ digital logic CMOS process. In this paper, the case of conventional asymmetric inductor, and vertical shunt symmetrical inductor with a relatively higher number of turns have been compared in order to efficient a size efficient CMOS LNA design method while still retaining the circuit operation characteristics.

• 한국정보통신설비학회:학술대회논문집
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• 2006.08a
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• pp.215-218
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• 2006

In this paper, a small size, $7{\times}6mm^2$, Low Noise Amplifier(LNA) using LTCC process was fabricated with multi-layer structure for 2.4GHz wireless LAN. The measured results demonstrate that the bandwidth is 130 MHz, and the operating frequency is from 2.39GHz to 2.52GHz. The power gain is above 7.3 dB in the operating frequency range and the gain flatness is 0.5 dB. The maximum S11 is -4 dB and the maximum S22 is -7.5 dB. The noise figure is less than 1.83 dB. The measured power gain, S11 and S22 were had poorer performance than the simulation results. The reason for this discrepancy is that the input and output matching was not performed exactly. However, the noise figure of the LTCC low noise amplifier is better than simulation result. It is found that it is possible to fabricate a LTCC low noise amplifier in a small size.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.426-432
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• 2012

A fully-integrated low power K-band radar transceiver in 130 nm CMOS process is presented. It consists of a low-noise amplifier (LNA), a down-conversion mixer, a power amplifier (PA), and a frequency synthesizer with injection locked buffer for driving mixer and PA. The receiver front-end provides a conversion gain of 19 dB. The LNA achieves a power gain of 15 dB and noise figure of 5.4 dB, and the PA has an output power of 9 dBm. The phase noise of VCO is -90 dBc/Hz at 1-MHz offset. The total dc power dissipation of the transceiver is 142 mW and the size of the chip is only $1.2{\times}1.4mm^2$.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.24 no.5
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• pp.682-685
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• 2020

In this paper, we analyze the dominant noise source of conventional inductively degenerated common-source (CS) cascode low noise amplifier (LNA) when width and gate length of stacked transistors vary. Analytical MOSFET and its noise model are used to estimate the contributions of noise sources. All parameters are based on measured data of 60nm, 90nm and 130nm CMOS devices. Based on the noise analysis for different frequencies and device parameters including process nodes, the dominant noise source can be analyzed to optimize noise figure on the configuration. We verified analytically that the intuctively degenerated CS topology can not sustain its benefits in noise above a certain operation frequency of LNA over different process nodes.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.10
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• pp.832-835
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• 2017

In this paper, V-band differential low noise amplifier(LNA) using 65-nm CMOS process for high speed wireless data communication is presented. The LNA is composed of 3-stage common-source differential amplifiers with neutralization of feedback capacitances using MOS capacitors and impedance matching utilizing transformers. The fabricated LNA has a peak gain of 23 dB at 63 GHz and 3 dB bandwidth of 6 GHz. The chip area of LNA is $0.3mm^2$ and the LNA consumes 32 mW DC power from 1.2 V supply voltage.

• International Journal of Contents
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• v.2 no.1
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• pp.29-33
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• 2006

The common-source low noise amplifier(LNA) with inductive degeneration using a genetic algorithm is designed and tested for a down converter in an industrial, scientific and medical (ISM) band application and a wireless broadband internet service (WiBro). The genetic algorithm optimizes the reflection coefficients to be well matched the input and output ports between multistage transistor amplifiers, and it generates low voltage standing wave ratio as well as gain flatness of the amplifier. The stability and the gain flatness of the LNA have been improved by combining the matching circuits and the series feedback microstrip lines with inductive degeneration at common-source port. In the frequency range of ISM band and WiBro application operating at $2.3GHz{\sim}2.5GHz$, the measured power gain and maximum voltage standing wave ratio (VSWR) of the LNA are $41{\pm}0.5dB$ and 1.3, and the noise figure of the LNA is lower than 0.85dB. The above results are agreed well with the theoretical values of the amplifiers.

• Journal of information and communication convergence engineering
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• v.15 no.2
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• pp.112-116
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• 2017

In this work, we demonstrated a low noise and high linearity low noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) with novel active bias circuit for LTE applications. The device technology used in this work relies on a process involving a $0.25-{\mu}m$ GaAs pseudomorphic high electron mobility transistor (PHEMT). The LNA MMIC with a novel active bias circuit has a small signal gain of $19.7{\pm}1.5dB$ and output third order intercept point (OIP3) of 38-39 dBm in the frequency range 1.75-2.65 GHz. The noise figure (NF) is less than 0.58 dB over the full bandwidth. Compared with the characteristics of the LNA MMIC without using the novel active bias circuit, the OIP3 is improved about 2-3 dBm. The small signal gain and NF showed no significant change after using the active bias circuit. The novel active bias circuit indeed improves the linearity performance of the LNA MMIC without degradation.