Journal of the Institute of Electronics Engineers of Korea SD (대한전자공학회논문지SD)

The Institute of Electronics and Information Engineers (대한전자공학회)
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Size-Efficient 3 GHz CMOS LNA

회로면적에 효율적인 3 GHz CMOS LNA설계

  • 전희석 (서울대학교 전기공학부, ISRC) ;
  • 윤여남 (서울대학교 전기공학부, ISRC) ;
  • 송익현 (서울대학교 전기공학부, ISRC) ;
  • 신형철 (서울대학교 전기공학부, ISRC)
  • Published : 2007.10.25
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Abstract

This paper presents the implementation technique to reduce circuit area occupation in designing Low Noise Amplifier (LNA) using vertical shunt symmetric inductor. We applied a vertical shunt symmetric inductor to match the input and output in 3 GHz CMOS LNA to reduce the circuit area. This size efficient amplifier has been designed in a $0.18\;{\mu}m$ digital logic CMOS process. In this paper, the case of conventional asymmetric inductor, and vertical shunt symmetrical inductor with a relatively higher number of turns have been compared in order to efficient a size efficient CMOS LNA design method while still retaining the circuit operation characteristics.

본 논문에서는 vertical shunt symmetric inductor를 이용하여 CMOS LNA의 설계에 있어서 회로의 면적을 줄이는 설계기술 및 구현에 관한 내용을 제시하고자 한다. 본 연구에 있어서 vertical shunt symmetric inductor는 LNA의 입력단과 출력단을 3GHz로 정합하기 위해서 사용되었다. 이렇게 구현된 보다 면적에 있어서 효율적인 증폭기를 0.18um digital logic공정으로 구현되었다. 본 논문에서는 일반적으로 LNA에서 사용하고 있는 inductor를 이용하는 경우와, vertical shunt symmetric inductor를 이용하여 LNA를 설계하는 경우에 대한 부분을 비교하였고, 최종적으로 면적에 효율적인 회로설계 기술을 제시하고자 한다.

Keywords

References

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