• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.278-281
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• 2000

In this study, the electrical characteristics of 100V -Class LDMOSFET for high temperature applications such as electronic control systems of automobiles and motor driver were investigated. Measurement data are taken over wide range of temperature(300K-500K) and various drift region length(6.6$\mu\textrm{m}$-12.6$\mu\textrm{m}$). In high temperature condition(>450K), drain current decreased over 50％, and specific on-resistance increased about twice in comparison with room temperature. Moreover the ratio R$\sub$on//BV, a figure of merit of the device, increased with increasing temperature.

• Transactions on Electrical and Electronic Materials
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• v.8 no.1
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• pp.21-25
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• 2007

A two-dimensional TCAD MEDICI simulator was used to examine the voltage transfer characteristics, on-off switching properties and latch-up of a CMOS inverter as a function of the n-channel length and doping levels. The channel in a LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of a CMOS inverter. The digital logic levels of the output and input voltages were analyzed from the transfer curves and circuit operation. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1077-1080
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• 2003

This paper show the measured result of electrical characteristics of SOI-LDMOSFET that is one of the high voltage devises. Especially, we observed changes of breakdown voltage, threshold voltage, on-resistance, drain current, and transconductance in accordance with drift length, main parameter of LDMOSFET. Also, we achieved reliability analysis about device operation in high temperature environment because LDMOS is applied to smart power IC.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1578-1580
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• 2002

The breakdown and on-state characteristics of the multi-RESURF SOI LDMOSFET is presented. P-/n-epi layer thickness and doping concentration is varied from $2{\mu}m{\sim}5{\mu}m$ and $1{\times}10^{15}/cm^3{\sim}9{\times}10^{15}/cm^3$ to obtain optimum breakdown voltage and on-resistance. The breakdown and on-state characteristics of the device is verified by two-dimensional process simulator ATHENA and device simulator ATLAS.

• Proceedings of the KIEE Conference
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• 2005.07c
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• pp.1957-1959
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• 2005

표면이 도핑된 SOI RESURF LDMOSFET에 대해 표면 도핑의 깊이에 따른 항복전압 및 순방향 특성을 분석하였다. 표면 도핑영역의 깊이를 $0.5{\sim}2.0{\mu}m$까지 변화시켜가며 항복전압의 변화와 온-저항의 변화를 시뮬레이션 하였다. 표면 도핑영역의 깊이에 따라 항복전압은 $73V{\sim}138V$까지 변화하였으며, 온-저항도 $0.18{\sim}0.143{\Omega}/cm^2$까지 변화하였다. 항복전압은 표면 도핑 영역의 깊이가 $1.5{\mu}m$때 138V로 가장 높게 나타났으며, 동일한 에피 영역의 농도를 사용한 기존의 소자와 비교하였을 때 약 22.1%의 항복전압의 증가를 나타냈으며, 온-저항값은 약 21.8%정도 감소하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.102-103
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• 2007

The electrical characteristics of high power LIGBT implemented by CMOS process are described and compared with those of high voltage LDMOSFET with the same device dimensions. LIGBT has exhibited approximately 8 times superior current drive capability than LDMOSFET. The proposed p+/n+ anode structure resulted in the significant increase of on-state breakdown voltage of LIGBT. Therefore, LIGBT suggested in this paper is one of the promising candidate for smart power IC applications.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.07a
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• pp.361-364
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• 2004

Surface doped SOI RESURF LDMOSFET with recessed source region is proposed to improve the on- and off-state characteristics. Surface region of the proposed LDMOS structure is doped like step. The characteristics of the proposed LDMOS is verified by two-dimensional process simulator ATHENA and device simulator ATLAS[1]. The numerically calculated on-resistance($R_{ON}$) of the proposed LDMOS is $10.36\Omega-cm$ and breakdown voltage is 205V when $L_{dr}=7{\mu}m$ with step doped surface.

• Journal of IKEEE
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• v.8 no.1 s.14
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• pp.152-159
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• 2004

In this study, we design the one-chip PWM IC with high voltage power switch (300V class LDMOSFET) for SMPS (Switching Mode Power Supply) application. Reference circuits generate constant voltage(5V) in the various of power supply and temperature condition. Error amp. is designed with large DC gain $({\simeq}65dB)$, unity frequency $({\simeq}190kHz)$ and large $PM(75^{\circ})$. comparator is designed with 2 stage. Saw tooth generators operate with 20kHz oscillation frequency. Also, we optimize drift concentration & drift length of n-LDMOSFET for design of high voltage switching device. It is shown that simulation results have the breakdown voltage of 350V. (using ISE-TCAD Simulation tool). PWM IC with power switching device is designed with 2um design rule and Bi-DMOS technology.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.509-512
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• 2004

This paper proposed a new solid State Relay(SSR) structure that can replace the conventional SSR as a power IC. The photodiode arrays, the main part of this structure, were designed and integrated in the same power It chip with the output parts, LDMOSFET and BJT, on a SOI substrate. The fabrication of this input part shared the same output LDMOSFET fabrication processs, except the additional deposition of Silicon nitride($Si_3N_4$) for the photo-detection part. According to LED illumination intensites and photo detecting areas, we could obtain voltage of 0.49V ${\~}$0.52V and current of 5.5uA ${\~}$ 108uA respectively from the fabricated unit photodiode. The maximum value of the voltage and the current we could obtain from the photodiode array were 3.58V and 24.4uA respectively, and the voltage was enough to operate the output LDMOSFET

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.17 no.9
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• pp.911-915
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• 2004

In this study, the electrical characteristics of high-voltage LDMOSFET fabricated by the existing CMOS technology were investigated depending on its process and design parameter. In order to verify the experimental data, two-dimensional device simulation was carried out simultaneously. The off- state breakdown voltages of n-channel LDMOSFETs were increased nearly in proportional to the drift region length. For the case of decreasing n-well ion implant doses from $1.0\times{10}^{13}/cm^2$ to $1.0\times{10}^{12}/cm^2$, the off-state breakdown voltage was increased approximately two times. The on-resistance was also increased about 76 %. From 2-D simulation, the increase in the breakdown voltage was attributed to a reduction in the maximum electric field of LDMOS imolanted with low dose as well as to a shift toward n+ drain region. Moreover, the on- and off-state breakdown voltages were also linearly increased with increasing the channel to n-tub spacing due to the reduction of impact ionization at the drift region. The experimental and design data of these high-voltage LDMOS devices can widely applied to design smart power ICs with low-voltage CMOS control and high-voltage driving circuits on the same chip.