• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.367-369
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• 1995

An SOI LDMOS(Silicon-On-Insulator Lateral Double diffused MOSPET) with a tapered field plate is proposed and investigated in terms of the breakdown voltage and on-resistance using 2-D simulator, MEDICI. The results of conventional SOI LDMOS with a stepped field plate are reported for the comparison. Simulated breakdown voltage of the proposed LDMOS is found to be higher than that of conventional LDMOS since surface electric field can be reduced due to the field plate over the tapered oxide. On-resistance of proposed LDMOS is found to be lower than that of conventional LDMOS by 10%.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.55 no.2
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• pp.72-75
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• 2006

A CMOS compatible Super Junction LDMOS (SJ-LDMOS) structure, which reduces substrate-assisted depletion effects, is reported. The proposed structure uses a N-buffer layer between the pillars and P-substrate to achieve global charge balance between the pillars, the N-buffer layer and the P-substrate. The new structure features high breakdown voltage, low on-resistance, and reduced sensitivity to doping imbalance in the pillars.

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1797-1799
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• 2000

A SOI LDMOS with trench drain and graded gate is proposed to improve the on resistance. The proposed structure can decrease the on resistance by reducing the path of electron current. Simulation results by SUPREM and MEDICI have shown that the on resistance of the LDMOS with trench drain and graded gate was 14.8 % lower than conventional LDMOS with graded gate.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.4
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• pp.484-491
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• 2008

In this paper, we design and fabricate the L-band high speed pulsed HPA using LDMOS FET. And we propose the high voltage and high speed switching circuit for LDMOS FET. The pulsed HPA using LDMOS FET is simpler than using GaAs FET because it has a high gain, high output power and sin81e voltage supply. LDMOS FET is suitable for pulsed HPA using switching method because it has $2{\sim}3$ times higher maximum drain-source voltage(65 V) than operating drain-source voltage($V_{ds}=26{\sim}28\;V$). As results of test, the output peak power is 100 W at 1.2 GHz, the rise/fall time of output RF pulse are 28.1 ns/26.6 ns at 2 us pulse width with 40 kHz PRF, respectively.

• Transactions on Electrical and Electronic Materials
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• v.10 no.6
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• pp.193-195
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• 2009

This paper aims to develop a low gate source voltage ($V_{gs}$) N-LDMOS element that is fully operational at a CMOS Logic Gate voltage (3.3 or 5 V) realized using the 0.35 μm BCDMOS process. The basic structure of the N-LDMOS element presented here has a Low $V_{gs}$ LDMOS structure to which the thickness of a logic gate oxide is applied. Additional modification has been carried out in order to obtain features of an improved breakdown voltage and a specific on resistance ($R_{sp}$). A N-LDMOS element can be developed with improved features of breakdown voltage and specific on resistance, which is an important criterion for power elements by means of using a proper structure and appropriate process modification. In this paper, the structure has been made to withstand the excessive electrical field on the drain side by applying the double gate oxide structure to the channel area, to improve the specific on resistance in addition to providing a sufficient breakdown voltage margin. It is shown that the resulting modified N-LDMOS structure with the feature of the specific on resistance is improved by 31%, and so it is expected that optimized power efficiencies and the size-effectiveness can be obtained.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1609-1611
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• 1996

The on-resistance characteristics of the RESURF LDMOS and VDMOS are compared. The on-resistance vs. breakdown characteristics of the RESURF LDMOS is analytically investigated. The on-resistance of RESVRF LDMOS is as almost same as that of VDMOS.

• Journal of IKEEE
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• v.27 no.4
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• pp.567-572
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• 2023

In this paper, the breakdown voltage of Pi-LDMOS (Partial isolation lateral double diffused metal oxide semiconductor) was analyzed by simulation. Breakdown voltage variation is investigated under various settings of Parial buied oxide(P-BOX) parameters(length, thickness, location) and their mechanism is specified. In addition, the change in on-resistance in the breakdown voltage and trade-off relationship was analyzed according to the change in the P-BOX parameter, and the Figure-of-merit(FOM) was calculated and compared. In proposed structure, Lbox=5 ㎛, tbox=2 ㎛, and Lbc=2 ㎛ showed the highest breakdown voltage of 138V, and Lbox=5 ㎛, tbox=1.6 ㎛, and Lbc=2 ㎛ showed the highest FOM. Compared to conventional LDMOS, the breakdown voltage is 123% and FOM is 3.89 times improved. Therefore, Pi-LDMOS has a high breakdown voltage and FOM, which can contribute to the improvement of the stable operating range of the Power IC.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.9
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• pp.605-610
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• 1999

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with a recessed source structure is proposed to improve the on-resistance and the breakdown voltage. The recessed source structure can decrease the on-resistance by reducing the path of electron current, also increase the breakdown voltage by extending the effective length of gate field plate. Simulation results by TSUPREM4 and MEDICI have shown that the on-resistance of the LDMOS with a recessed source was 26% lower than conventional LDMOS. The breakdown voltage of proposed device was found to be 45V while that of conventional device was 36.5 V. At the same breakdown voltage of 36.5V, the on-resistance of the LDMOS with a recessed source was 41% lower than that of conventional structure.

• Journal of Advanced Marine Engineering and Technology
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• v.30 no.8
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• pp.901-906
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• 2006

In this paper, the power amplifier using active bias circuits for LDMOS(Lateral Diffused Metal Oxide Semiconductor) MRF-21180 is designed and fabricated. According to change the temperature, the gate voltage of LDMOS is controlled by the fabricated active bias circuits which is made of PNP transistor to suppress drain current. The driving amplifier using MRF-21125 and MRF-21060 is made to drive the LDMOS MRF-21180 power amplifier. The variation of current consumption in the fabricated 60 watt power amplifier has an excellent characteristics of less than 0.1 A, whereas a passive biasing circuit dissipates more than 0.5 A. The implemented power amplifier has the gain over 9 dB, the gain flatness of less than $\pm$0.1 dB and input and output return loss of less than -6 dB over the frequency range 2.11 $\sim$ 2.17 GHz. The DC operation point of this power amplifier at temperature variation 0 $^{\circ}C$ to 60 $^{\circ}C$ is fixed by active bias circuit.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.163-165
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• 2002

LDD구조를 가진 LDMOS 전력소자의 LDD영역과 채널영역변화에 의한 전기적 특성을 비교 조사하였다. MEDICI 시뮬레이션 tool을 이용하여 hot-carrier전류의 특성, ON 저항의 변화, breakdown 전압의 특성과 switch transient 특성을 조사하였다. Gate-drain 사이의 불순물도핑 영역 및 농도에 따른 소자의 특성해석은 LDD구조를 가진 LDMOS가 hot-carrier resistance 및 전력소모 관점에서 우수한 특성을 나타낼 것으로 사료된다