• 대한전기학회:학술대회논문집
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• 대한전기학회 1995년도 추계학술대회 논문집 학회본부
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• pp.367-369
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• 1995

An SOI LDMOS(Silicon-On-Insulator Lateral Double diffused MOSPET) with a tapered field plate is proposed and investigated in terms of the breakdown voltage and on-resistance using 2-D simulator, MEDICI. The results of conventional SOI LDMOS with a stepped field plate are reported for the comparison. Simulated breakdown voltage of the proposed LDMOS is found to be higher than that of conventional LDMOS since surface electric field can be reduced due to the field plate over the tapered oxide. On-resistance of proposed LDMOS is found to be lower than that of conventional LDMOS by 10%.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제55권2호
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• pp.72-75
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• 2006

A CMOS compatible Super Junction LDMOS (SJ-LDMOS) structure, which reduces substrate-assisted depletion effects, is reported. The proposed structure uses a N-buffer layer between the pillars and P-substrate to achieve global charge balance between the pillars, the N-buffer layer and the P-substrate. The new structure features high breakdown voltage, low on-resistance, and reduced sensitivity to doping imbalance in the pillars.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 하계학술대회 논문집 C
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• pp.1797-1799
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• 2000

A SOI LDMOS with trench drain and graded gate is proposed to improve the on resistance. The proposed structure can decrease the on resistance by reducing the path of electron current. Simulation results by SUPREM and MEDICI have shown that the on resistance of the LDMOS with trench drain and graded gate was 14.8 % lower than conventional LDMOS with graded gate.

• 한국전자파학회논문지
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• 제19권4호
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• pp.484-491
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• 2008

본 논문에서는 LDMOS FET를 이용하여 스위칭 방식의 L-대역 고속 펄스 고전력 증폭기를 설계하고 제작하였다. 이를 위해 LDMOS FET의 드레인 전원을 스위칭하기 위한 고전압 스위칭 회로를 제안하였다. LDMOS FET를 이용한 펄스 고전력 증폭기는 단일 전원을 사용하고, 소자 특성상 이득과 출력이 높기 때문에 기존의 GaAs FET를 사용한 증폭기에 비해 구조가 간단하며, 사용 전압($V_{ds}=26{\sim}28\;V$)에 비해 최대 허용 전압(65 V)이 $2{\sim}3$배 높아 스위칭 방식에 적합하다. LDMOS FET를 이용하여 제작된 1.2 GHz 대역 100 W 펄스 증폭기는 펄스 폭이 2 us, PRF가 40 kHz의 출력 신호에서 상승 시간이 28.1 ns, 하강 시간이 26.6 ns로 측정되었다.

• Transactions on Electrical and Electronic Materials
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• 제10권6호
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• pp.193-195
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• 2009

This paper aims to develop a low gate source voltage ($V_{gs}$) N-LDMOS element that is fully operational at a CMOS Logic Gate voltage (3.3 or 5 V) realized using the 0.35 μm BCDMOS process. The basic structure of the N-LDMOS element presented here has a Low $V_{gs}$ LDMOS structure to which the thickness of a logic gate oxide is applied. Additional modification has been carried out in order to obtain features of an improved breakdown voltage and a specific on resistance ($R_{sp}$). A N-LDMOS element can be developed with improved features of breakdown voltage and specific on resistance, which is an important criterion for power elements by means of using a proper structure and appropriate process modification. In this paper, the structure has been made to withstand the excessive electrical field on the drain side by applying the double gate oxide structure to the channel area, to improve the specific on resistance in addition to providing a sufficient breakdown voltage margin. It is shown that the resulting modified N-LDMOS structure with the feature of the specific on resistance is improved by 31%, and so it is expected that optimized power efficiencies and the size-effectiveness can be obtained.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1609-1611
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• 1996

The on-resistance characteristics of the RESURF LDMOS and VDMOS are compared. The on-resistance vs. breakdown characteristics of the RESURF LDMOS is analytically investigated. The on-resistance of RESVRF LDMOS is as almost same as that of VDMOS.

• 전기전자학회논문지
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• 제27권4호
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• pp.567-572
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• 2023

본 논문에서는 Partial isolation lateral double diffused metal oxide semiconductor(Pi-LDMOS)의 항복전압에 대해 시뮬레이션을 통해 분석하였다. 항복전압 변화는 Partial buried oxide(P-BOX)의 다양한 파라미터(길이, 두께, 위치)에 따라 조사되었고, 그 메커니즘에 대해 명기하였다. 또한 항복전압과 trade-off 관계에 있는 온저항의 변화를 P-BOX 파라미터 변화에 따라 분석하였고 Figure of merit(FOM)을 계산하여 비교하였다. 제안된 구조에서 L_box=5㎛, t_box=2㎛, L_bc=2㎛일 경우 138V의 가장 높은 항복전압을 나타내었고, L_box=5㎛, t_box=1.6㎛, L_bc=2㎛일 경우 가장 높은 FOM을 나타내었다. 이는 conventional LDMOS 대비 항복전압은 123%, FOM은 3.89배 향상된 수치이다. 따라서 Pi-LDMOS는 높은 항복전압과 FOM을 가져 Power IC의 안정적인 동작범위 향상에 기여할 수 있다.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제48권9호
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• pp.605-610
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• 1999

An SOI(Silicon-On-Insulator) LD(Lateral Double-diffused)MOS with a recessed source structure is proposed to improve the on-resistance and the breakdown voltage. The recessed source structure can decrease the on-resistance by reducing the path of electron current, also increase the breakdown voltage by extending the effective length of gate field plate. Simulation results by TSUPREM4 and MEDICI have shown that the on-resistance of the LDMOS with a recessed source was 26% lower than conventional LDMOS. The breakdown voltage of proposed device was found to be 45V while that of conventional device was 36.5 V. At the same breakdown voltage of 36.5V, the on-resistance of the LDMOS with a recessed source was 41% lower than that of conventional structure.

• Journal of Advanced Marine Engineering and Technology
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• 제30권8호
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• pp.901-906
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• 2006

In this paper, the power amplifier using active bias circuits for LDMOS(Lateral Diffused Metal Oxide Semiconductor) MRF-21180 is designed and fabricated. According to change the temperature, the gate voltage of LDMOS is controlled by the fabricated active bias circuits which is made of PNP transistor to suppress drain current. The driving amplifier using MRF-21125 and MRF-21060 is made to drive the LDMOS MRF-21180 power amplifier. The variation of current consumption in the fabricated 60 watt power amplifier has an excellent characteristics of less than 0.1 A, whereas a passive biasing circuit dissipates more than 0.5 A. The implemented power amplifier has the gain over 9 dB, the gain flatness of less than $\pm$0.1 dB and input and output return loss of less than -6 dB over the frequency range 2.11 $\sim$ 2.17 GHz. The DC operation point of this power amplifier at temperature variation 0 $^{\circ}C$ to 60 $^{\circ}C$ is fixed by active bias circuit.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2002년도 전력전자학술대회 논문집
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• pp.163-165
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• 2002

LDD구조를 가진 LDMOS 전력소자의 LDD영역과 채널영역변화에 의한 전기적 특성을 비교 조사하였다. MEDICI 시뮬레이션 tool을 이용하여 hot-carrier전류의 특성, ON 저항의 변화, breakdown 전압의 특성과 switch transient 특성을 조사하였다. Gate-drain 사이의 불순물도핑 영역 및 농도에 따른 소자의 특성해석은 LDD구조를 가진 LDMOS가 hot-carrier resistance 및 전력소모 관점에서 우수한 특성을 나타낼 것으로 사료된다