Journal of IKEEE (전기전자학회논문지)

Institute of Korean Electrical and Electronics Engineers (한국전기전자학회)
권호 표지
DOI QR코드

DOI QR Code

Breakdown Voltage and On-resistance Analysis of Partial-isolation LDMOS

Partial-isolation LDMOS의 항복전압과 온저항 분석

  • Sin-Wook Kim (Department of ICT Convergence System Engineering, Chonnam National University) ;
  • Myoung-jin Lee (Department of ICT Convergence System Engineering, Chonnam National University)
  • Received : 2023.12.04
  • Accepted : 2023.12.26
  • Published : 2023.12.31
Download PDF
⟨ Previous Next ⟩

Abstract

In this paper, the breakdown voltage of Pi-LDMOS (Partial isolation lateral double diffused metal oxide semiconductor) was analyzed by simulation. Breakdown voltage variation is investigated under various settings of Parial buied oxide(P-BOX) parameters(length, thickness, location) and their mechanism is specified. In addition, the change in on-resistance in the breakdown voltage and trade-off relationship was analyzed according to the change in the P-BOX parameter, and the Figure-of-merit(FOM) was calculated and compared. In proposed structure, Lbox=5 ㎛, tbox=2 ㎛, and Lbc=2 ㎛ showed the highest breakdown voltage of 138V, and Lbox=5 ㎛, tbox=1.6 ㎛, and Lbc=2 ㎛ showed the highest FOM. Compared to conventional LDMOS, the breakdown voltage is 123% and FOM is 3.89 times improved. Therefore, Pi-LDMOS has a high breakdown voltage and FOM, which can contribute to the improvement of the stable operating range of the Power IC.

본 논문에서는 Partial isolation lateral double diffused metal oxide semiconductor(Pi-LDMOS)의 항복전압에 대해 시뮬레이션을 통해 분석하였다. 항복전압 변화는 Partial buried oxide(P-BOX)의 다양한 파라미터(길이, 두께, 위치)에 따라 조사되었고, 그 메커니즘에 대해 명기하였다. 또한 항복전압과 trade-off 관계에 있는 온저항의 변화를 P-BOX 파라미터 변화에 따라 분석하였고 Figure of merit(FOM)을 계산하여 비교하였다. 제안된 구조에서 Lbox=5㎛, tbox=2㎛, Lbc=2㎛일 경우 138V의 가장 높은 항복전압을 나타내었고, Lbox=5㎛, tbox=1.6㎛, Lbc=2㎛일 경우 가장 높은 FOM을 나타내었다. 이는 conventional LDMOS 대비 항복전압은 123%, FOM은 3.89배 향상된 수치이다. 따라서 Pi-LDMOS는 높은 항복전압과 FOM을 가져 Power IC의 안정적인 동작범위 향상에 기여할 수 있다.

Keywords

Acknowledgement

This research was supported by the MSIT(Ministry of Science and ICT), Korea, under the ICAN(ICT Challenge and Advanced Network of HRD) program(IITP-2023-RS-2022-00156385) supervised by the IITP(Institute of Information & Communications Technology Planning & Evaluation). This research was supported by the MSIT(Ministry of Science and ICT), Korea, under the Innovative Human Resource Development for Local Intellectualization support program(IITP-2023-RS-2022-00156287) supervised by the IITP(Institute for Information & communications Technology Planning & Evaluation). This research was supported by the BK21 FOUR Program(Fostering Outstanding Universities for Research, 5199991 714138) funded by the Ministry of Education (MOE, Korea) and National Research Foundation of Korea(NRF). The EDA tool was supported by the IC Design Education Center (IDEC), South Korea.

References

  1. K. S. Nikhil, N. DasGupta, A. DasGupta and A. Chakravorty, "Analysis and Modeling of the Snapback Voltage for Varying Buried Oxide Thickness in SOI-LDMOS Transistors," in IEEE Transactions on Electron Devices, vol.63, no.10, pp.4003-4010, 2016. DOI: 10.1109/TED.2016.2600265.
  2. K. S. Nikhil, N. DasGupta, A. DasGupta and A. Chakravorty, "SOI-LDMOS Transistors With Optimized Partial n+ Buried Layer for Improved Performance in Power Amplifier Applications," in IEEE Transactions on Electron Devices, vol.65, no.11, pp.4931-4937, 2018. DOI: 10.1109/TED.2018.2867656.
  3. Myoung Jin Lee et al., "Partial SOI type isolation for improvement of DRAM cell transistor characteristics," in IEEE Electron Device Letters, vol.26, no.5, pp.332-334, 2005, DOI: 10.1109/LED.2005.846590.
  4. J. H. Park et al., "Row Hammer Reduction Using a Buried Insulator in a Buried Channel Array Transistor," in IEEE Transactions on Electron Devices, vol.69, no.12, pp.6710-6716, 2022. DOI: 10.1109/TED.2022.3215931.
  5. Y. Hu et al., "Dimension Effect on Breakdown Voltage of Partial SOI LDMOS," in IEEE Journal of the Electron Devices Society, vol. 5, no. 3, pp. 157-163, 2017. DOI: 10.1109/JEDS.2017.2690363.
  6. A. A. Orouji, S. Sharbati and M. Fathipour, "A New Partial-SOI LDMOSFET With Modified Electric Field for Breakdown Voltage Improvement," in IEEE Transactions on Device and Materials Reliability, vol.9, no.3, pp.449-453, 2009. DOI: 10.1109/TDMR.2009.2024688.
  7. S. E. Jamali Mahabadi, A. A. Orouji, P. Keshavarzi, S. Rajabi, Hamid Amini Moghadam and Maryam Iranian Pour Haghighi, "A novel step buried oxide Partial SOI LDMOSFET with Triple Drift layer," 2011 International Conference on Signal Processing, Communication, Computing and Networking Technologies, Thuckalay, India, 2011, pp.174-177. DOI: 10.1109/ICSCCN.2011.6024538.
  8. H. Elahipanah and A. A. Orouji, "A 1300-V 0.34-Ω·cm2 Partial SOI LDMOSFET With Novel Dual Charge Accumulation Layers," in IEEE Transactions on Electron Devices, vol.57, no.8, pp.1959-1965, 2010. DOI: 10.1109/TED.2010.2050100.
  9. Garner DM, Ensell G, Bonar J, Blackburn A, Udrea F,Lim HT, et al. The fabrication of a partial SOI substrate. In: Ninth International Symposium on Silicon-on-Insulator Technology and Devices, 1999. pp.73-8.
  10. Houadef, Ali, and Boualem Djezzar. 2022. "Design of an LDMOS Transistor Based on the 1 µm CMOS Process for High/Low Power Applications" Engineering Proceedings 14, no.1: 17. http DOI: 10.3390/engproc2022014017
  11. J. A. Appels and H. M. J. Vaes, "High voltage thin layer devices (RESURF devices)," 1979 International Electron Devices Meeting, Washington, DC, USA, 1979, pp.238-241, DOI: 10.1109/IEDM.1979.189589.
  12. J. Yaoet al., "SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions," in IEEE Transactions on Electron Devices, vol.70, no.5, pp.2204-2209, 2023. DOI: 10.1109/TED.2023.3262224.