• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.910-917
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• 2009

We have designed a new structures of Junction Field Effect Transistor(JFET) using SILVACO simulation to improve electrical properties and process reliability. The device structure and process conditions of Si control JFET(Si JFET) were determined to set cut off voltage and drain current(at Vg=0 V) to -0.46 V and $300\;{\mu}A$, respectively. Among many design parameters influencing the performance of the device, the drive-in time of p-type gate is presented most predominant effects. Therefore we newly designed SiGe JFET, in which SiGe layers were placed above and underneath of Si-channel. The presence of SiGe layer could lessen Boron into the n-type Si channel, so that it would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer could be explained in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.5
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• pp.29-34
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• 1977

Using JFET and bipolar transistor, we have designed a circuit of current controlled negative resitance and analysed this circuit in the operating region. Since the positive gate voltage of N-channel JFET is applied in full operating region, the output and transfer characteristics of JFET are measured in the positive gate region. The performances of this circuit are predicted from these characteristics and experimental results of the proposed CCNR circuit are presented.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.22 no.11
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• pp.905-909
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• 2009

The new Junction Field Effect Transistors (JFETs) with Silicon-germanium (SiGe) layers is investigated. This structure uses SiGe layer to prevent out diffusion of boron in the channel region. In this paper, we report electrical properties of SiGe JFET measured under various design parameters influencing the performance of the device. Simulation results show that out diffusion of boron is reduced by the insertion SiGe layers. Because the SiGe layer acts as a barrier to prevent the spread of boron. This proposed JFET, regardless of changes in fabrication processes, accurate and stable cutoff voltage can be controlled. It is easy to maintain certain electrical characteristics to improve the yield of JFET devices.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.10
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• pp.29-34
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• 1992

JFET's with gate lengths ranging from 1$\mu$m to 8.3$\mu$m are successfully fabricated on InP substrate where the long haul (1.3$\mu$m~8.3$\mu$m) OEIC's(OptoElectronic Integrated Circuits) have been made. The pn junction of InP JFET's is made by co-implantation and RTA process. JFET's have etched-mesa-gate structure and the maximum gm larger than 90mS/mm was measured and this is the highest record in JFET's of such structure without S/D n$^{+}$ ion implantation. To maintain maximum g$_m$ should be well controlled the overetch of n-layer which inevitably occurs during etching off the unused p-layer. The I-V characteristic is checked during p-layer etch, for this purpose. A dc voltage gain of 11 is obtained from a preamplifier circuit thus fabricated.

• Journal of IKEEE
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• v.22 no.2
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• pp.339-343
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• 2018

Power semiconductors are semiconductors capable of controlling power over 1W and are mainly used as switches. This power semiconductor device has been developed with the goal of reducing power consumption and high breakdown voltage. This research was analyzed electrical characteristics of IGBT(Insulated Gate Biopolar Transistor) according to diffusion length of JFET region. The Diffusion length of JFET region was controlled by temperature and time using T-CAD simulator. As a result of experiments, we could obtain 1.14V low on state voltage drop by fixing 1440V breakdown voltage.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.04b
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• pp.37-38
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• 2009

SiC power device possesses attractive features, such as high breakdown voltage, high-speed switching capability, and high temperature operation. In general, device design has a significant effect on the switching characteristics. It is known that in SiC power MOSFET, the JFET region width is one of the most important parameters. In this paper, we demonstrated that the switching performance of DMOSFET is dependent on the with width of the JFET region by using 2-D Mixed-mode simulations. The 4H-SiC DMOSFETs with a JFET region designed to block 800 V were optimized for minimum loss by adjusting the parameters of the n JFET region, CSL, and n-drift layer. It has been found that the JFET region reduces specific on-resistance and therefore the switching characteristics depend on the JFET region.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.28 no.4
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• pp.213-217
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• 2015

Device model parameters are very important for accurate estimation of electrical performances in devices, integrated circuits and their systems. There are a large number of methods for extraction of model parameters in power MOSFETs. For high efficiency, design is important considerations of a power MOSFET with high-voltage applications in consumer electronics. Meanwhile, it was proposed that the efficiency of a MOSFET can be enhanced by conducting JFET region double implant to reduce the On-resistance of the transistor. This paper reports the effects of JFET region double implant on the electrical properties and the decreasing On-resistance of the MOSFET. Experimental results show that the 1st JFET region implant diffuse can enhance the On-resistance by decreasing the ion concentration due to the surface and reduce the On-resistance by implanting the 2nd Phosphorus to the surface JFET region.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.138-139
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• 2007

탄화규소반도체소자는 wide band-gap 반도체 재료로 고전압, 고속스위칭 특성이 우수하여 차세대 전력반도체소자로 매우 유망한 소자이다. 이러한 물리적 특성으로 전력변환소자인 고전압 MOSFET 소자를 개발하기 위한 연구가 활발히 진행되고 있다. 그러나 MOS 소자에서 가장 중요한 게이트 산화막의 특성이 소자에 적용하기에는 그 특성이 많이 취약한 상태이다. 따라서 이러한 단점을 해결하여 고전압 전력변환소자로 적용하기 위하여 게이트 산화막이 필요없는 JFET 소자가 많이 연구되고 있다. 본 논문에서는 JFET 소자를 normally-off type으로 동작시키기 위하여 게이트의 구조, 도핑농도 및 게이트 폭을 조절하여 simulation를 수행하였다. 케이트의 농도 및 접합깊이에 따라 normally-on 또는 off 특성에 큰 영향을 미치고 있으며 게이트 트렌치구조의 깊이에 따라서도 영향을 받는다. 본 simulation 결과 최적의 트렌치 길이, 폭 및 농도로 소자를 구성하여 $1.3m{\Omega}cm^2$의 온-저항 특성을 얻을 수 있었다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.626-626
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• 2013

P-N 접합에 의해 절연된 게이트를 통해 전류 통로를 제어하는 접합형 전계효과 트랜지스터(Junction Field Effect Transistors; JFETs)는, 입력 임피던스가 크고, 온도에 덜 민감하며, 제조가 간편하여 집적회로(IC) 제조가 용이하고, 동작의 해석이 단순하다는 장점을 가지고 있다. 특히 JFET는 선형적인 전류의 증폭 특성을 가지고 있으며, 잡음이작기 때문에, 감도가 우수한 음향 센서의 증폭회로, 선형성이 우수한 증폭회로, 입력 계측 증폭 회로 등에 주로 사용되고 있다. 기존에 사용되는 JFET 소자는 구조와 제조 공정에 따라서, 컷 오프 전압($V_{cut-off}$)과 드레인-소스 포화 전류($I_{DSS}$)의 변화가 심하게 발생하여, 소자의 전기적 특성 제어가 어렵고, 소자의 수율이 낮다는 문제점이 있다. 본 연구에서는 TCAD 시뮬레이션을 통해 게이트 전압에 의해 채널이 형성되는 채널 층의 상하부에 각각 $Si_xGe_{1-x}$로 이루어진 상부 및 하부 확산 저지층을 삽입한 JFET 소자 형성하여, 게이트 접합부의 접합 영역 확산을 저지하고, 상기 게이트 접합부가 계면에서 날카로운 농도 구배를 갖도록 함으로써, 공정 변화에 따른 전기적 특성의 편차가 작아지는 JFET 소자 구조를 만들어 전기적 특성을 개선하였다. JFET은 채널층에 삽입된 $Si_xGe_{1-x}$ 층의 두께, Ge 함유량 및 n채널층의 두께를 변화하였을 때, off 상태의 게이트-소스 전압이 감소한 반면에 드레인-소스 포화 전류($I_{DSS}$)와 컨덕턴스(gm) 값이 증가하였다. 삽입된 $Si_xGe_{1-x}$층이 Boron이 밖으로 확산되는 현상이 감소하여 채널이 좁아지는 현상을 막아 소자의 전기적 특성을 개선함으로써 제조공정의 변화에 관계없이 컷오프 전압을 정확하고 안정되게 제어할 수 있고 이를 통해 소자의 수율을 높일 수 있을 것으로 기대된다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.11a
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• pp.94-94
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• 2008

We have performed simulation for Junction Field Effect Transistor(JFET) using Silvco to improve its electrical properties. The device structure and process conditions of Si-control JFET(Si-JFET) were determined to set its cut off voltage and drain current(at Vg=0V) to -0.5V and $300{\mu}A$, respectively. From electrical property obtained at various implantation energy, dose, and drive-in conditions of p-gate doping, we found that the drive in time of p-type gate was the most determinant factor due to severe diffusion. Therefore we newly designed SiGe-JFET, in which SiGe layer is to epitaxial layers placed above and underneath of the Si-channel. The presence of SiGe layer lessen the p-type dopants (Boron) into the n-type Si channel the phenomenon would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer will be discussed in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.