Browse > Article
http://dx.doi.org/10.4313/JKEM.2015.28.4.213

Properties of Reducing On-resistance for JFET Region in Power MOSFET by Double Ion Implantation  

Kim, Ki Hyun (R&D Center, Maple Semiconductor Inc.)
Kim, Jeong Han (R&D Center, Maple Semiconductor Inc.)
Park, Tae-Su (R&D Center, Maple Semiconductor Inc.)
Jung, Eun-Sik (R&D Center, Maple Semiconductor Inc.)
Yang, Chang Heon (R&D Center, Maple Semiconductor Inc.)
Publication Information
Journal of the Korean Institute of Electrical and Electronic Material Engineers / v.28, no.4, 2015 , pp. 213-217 More about this Journal
Abstract
Device model parameters are very important for accurate estimation of electrical performances in devices, integrated circuits and their systems. There are a large number of methods for extraction of model parameters in power MOSFETs. For high efficiency, design is important considerations of a power MOSFET with high-voltage applications in consumer electronics. Meanwhile, it was proposed that the efficiency of a MOSFET can be enhanced by conducting JFET region double implant to reduce the On-resistance of the transistor. This paper reports the effects of JFET region double implant on the electrical properties and the decreasing On-resistance of the MOSFET. Experimental results show that the 1st JFET region implant diffuse can enhance the On-resistance by decreasing the ion concentration due to the surface and reduce the On-resistance by implanting the 2nd Phosphorus to the surface JFET region.
Keywords
MOSFET; Ion implant; On-resistance; Junction field area; JFET implant;
Citations & Related Records
연도 인용수 순위
  • Reference
1 G. Borionetti, D. Gambaro, S. Santi, M. Borgini, P. Godio, and S. Pizzini, Mater. Sci. Eng. B, B73, 218 (2000).
2 D. K. Schroder (New Jersey Wiley, Hoboken, 2006).
3 A. Michez, J. Boch, S. Dhombres, and F. Saigne, Microelectron Reliab., 53, 1306 (2013).   DOI
4 H. Chen, B. Ji, V. Pickert, and W. Cao, IEEE Trans Dev Mater Reliab, 14, 220 (2014).   DOI
5 Y. Ozcelep and A. Kuntman, Microelectron Int., 29, 141 (2012).   DOI
6 K. N. Quader, C. C. Li, R. Tu, E. Rosenbaum, P. K. Ko, and C. Hu, IEEE Trans Electron Dev., 40, 2245 (1993).   DOI
7 R. Habchi, C. Salame, P. Mialhe, and A. Khoury, Microelectron Reliab, 47, 1296 (2007).   DOI
8 B. Bernoux, R. Escoffier, and P. Jalbaud, IEEE International Symposium on Industrial Electronics, 2016 (2009).
9 F. Djahli, M. Bouchemat, and M. Kahouadji, Microelectron J, 31, 333 (1999).
10 M. R. Seacrist, Gate Dielectric Integrity: Material Process and Tool Qualification, 102 (2000).
11 J. Niccol, Solid State Phenomena, 145, 155 (2009).
12 D. Ueda, H. Takagi, and G. Kano, IEEE Trans Electron Dev., ED-32, 2 (1985).
13 W. S. Tam, S. L. Siu, B. L. Yang, C. W. Kok, and H. Wong, Microelectronics Reliability, 51, 2064 (2011).   DOI
14 S. Kumar and S. Jha, Microelectronics Journal, 44, 884 (2013).
15 E. Pomes, J. M. Reynes, P. Tounsia, and J. M. Dorkel, Materials Science and Engineering: B, 177, 1362 (2012).   DOI