Journal of the Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회논문지)

The Korean Institute of Electrical and Electronic Material Engineers (한국전기전자재료학회)
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Properties of Reducing On-resistance for JFET Region in Power MOSFET by Double Ion Implantation

JFET 영역의 이중이온 주입법을 이용한 Power MOSFET의 온저항 특성에 관한 연구

  • 김기현 (메이플세미컨덕터 신사업본부) ;
  • 김정한 (메이플세미컨덕터 신사업본부) ;
  • 박태수 (메이플세미컨덕터 신사업본부) ;
  • 정은식 (메이플세미컨덕터 신사업본부) ;
  • 양창헌 (메이플세미컨덕터 신사업본부)
  • Received : 2015.02.03
  • Accepted : 2015.03.19
  • Published : 2015.04.01
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Abstract

Device model parameters are very important for accurate estimation of electrical performances in devices, integrated circuits and their systems. There are a large number of methods for extraction of model parameters in power MOSFETs. For high efficiency, design is important considerations of a power MOSFET with high-voltage applications in consumer electronics. Meanwhile, it was proposed that the efficiency of a MOSFET can be enhanced by conducting JFET region double implant to reduce the On-resistance of the transistor. This paper reports the effects of JFET region double implant on the electrical properties and the decreasing On-resistance of the MOSFET. Experimental results show that the 1st JFET region implant diffuse can enhance the On-resistance by decreasing the ion concentration due to the surface and reduce the On-resistance by implanting the 2nd Phosphorus to the surface JFET region.

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References

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