• 제목/요약/키워드: Is-Spice

검색결과 478건 처리시간 0.023초

S-파라미터 측정을 통한 MOSFET 캐리어 속도의 고온 종속 SPICE 모델링 (High Temperature Dependent SPICE Modeling for Carrier Velocity in MOSFETs Using Measured S-Parameters)

  • 정대현;고봉혁;이성현
    • 대한전자공학회논문지SD
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    • 제46권12호
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    • pp.24-29
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    • 2009
  • $0.18{\mu}m$ deep n-well 벌크 NMOSFET에서 측정된 차단주파수 $f_T$의 고온종속성을 모델화하기 위해, 측정된 S-파라미터를 사용한 정확한 RF 방법으로 $30^{\circ}C$에서 $250^{\circ}C$까지 전자속도 고온 데이터가 추출되었다. 이러한 추출데이터를 사용하여 개선된 온도종속 전자속도 방정식이 높은 온도의 범위에서 생기는 기존 방정식의 모델링 오차를 없애기 위해 개발되었으며 BSIM3v3 SPICE RF 모델에 구현되었다. 개선된 온도 종속 방정식은 기존 모델보다 $30^{\circ}C$에서 $250^{\circ}C$까지 측정된 $f_T$와 더 잘 일치하였으며, 이는 개선된 방정식의 정확성을 입증한다.

철도분야 소프트웨어로의 SPICE 적용연구 (A Study on the Adoption of SPICE in the Railway Software)

  • 정의진;신경호
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 2006년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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    • pp.316-318
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    • 2006
  • It can be considered that the safety of software is combined with that of hardware, and also directly connected to system safety. Because the software in the railway system takes the form of Embedded that let it behave at the system level, instead of independent operation, the safety of the railway S/W is also important. The approach, for ensuring the quality and safety of those software, can be considered with two points of view. Those are views seeing from products, and from processes. The two points of approach are all necessary in the railway system. For the first of all, the process approach is to validate maturity of the organizations in accordance to the judging processes of organizations, which are specified by CMMI(Capability Maturity Model Integration) or SPICE(Software Process Improvement and Capability dEtermination: ISO/IECl5504). In this paper, as the first step of them, we are trying to find approaches to estimate the maturity of manufacturer and assessment organization in the railway system.

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박막트랜지스터의 문턱전압 이동 시뮬레이션 방안 (Simulation Method of Threshold Voltage Shift in Thin-film Transistors)

  • 정태호
    • 한국전기전자재료학회논문지
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    • 제26권5호
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    • pp.341-346
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    • 2013
  • Threshold voltage shift caused by trapping and release of charge carriers in a thin-film transistor (TFT) is implemented in AIM-SPICE tool. Turning on and off voltages are alternatively applied to a TFT to extract charge trapping and releasing process. Each process is divided into sequentially ordered processes, which are numerically modeled and implemented in a computer language. The results show a good agreement with the experimental data, which are modeled. Since the proposed method is independent of TFT's behavior models implemented in SPICE tools, it can be easily added to them.

IsSpice를 이용한 대화면 LCD 백라이트 CCFL 모델링 (Modeling of CCFL for the Large Screen LCD Backlight using IsSpice)

  • 박홍순;이정운;양승학;임영철;윤창선
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2007년도 하계학술대회 논문집
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    • pp.503-505
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    • 2007
  • 효율적인 LCD Backlight 구동 시스템 설계를 위해서는 CCFL에 대한 전기적 특성 파악이 중요하지만 디스플레이의 대형화에 따라 LCD Backlight 램프는 길어지고 비선형 특성으로 인해 특성 표현이 곤란하여 회로 설계시 간략화된 등가 모델을 사용하게 되어 실제 인버터 제작과정에서 많은 시행착오를 거치게 한다. 회로 설계시 수식모델 적용을 위한 CCFL의 모델이 필요하며, 이러한 모델은 인버터를 효율적으로 설계할 수 있게 하므로서 설계에 필요한 시간과 자원 절감을 가능하게 한다. 본 논문에서는 42인치 LCD 구동인버터 설계에 필요한 CCFL의 수식 모델링을 IsSpice를 이용하여 구현하였으며, 회로 시뮬레이션과 실험을 통하여 모델의 타당성을 검증하였다.

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단전자 트랜지스터로 구성된 논리 게이트 특성에 관한 연구 (A Study of Single Electron Transistor Logic Characterization Using a SPICE Macro-Modeling)

  • 김경록;김대환;이종덕;박병국
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2000년도 하계종합학술대회 논문집(2)
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    • pp.111-114
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    • 2000
  • Single Electron Transistor Logic (SETL) can be characterized by HSPICE simulation using a SPICE macro model. First, One unit SET is characterized by Monte-carlo simulation and then we fit SPICE macro-modeling equations to its characteristics. Second, using this unit SET, we simulate the transient characteristics of two-input NAND gate in both the static and dynamic logic schemes. The dynamic logic scheme shows more stable operation in terms of logic-swing and on/off current ratio. Also, there is a merit that we can use the SET only as current on-off switch without considering the voltage gain.

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SPICE를 이용한 GTO의 단일 운전과 스너버의 영향 (Single Operation of GTO's and Effect of Snubber Using SPICE)

  • 김윤호;윤병도;이장선
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1992년도 하계학술대회 논문집 B
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    • pp.1012-1015
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    • 1992
  • A gate-turn-off thyristor (GTO) that has a fuction of self-commutation is a device that can be turned on like a thyristor with a single pulse of gate current and turned-off by injecting a negative gate current pulse. GTOs have been in existence almost from the beginning of thyristor era, recently are these devices being developed with large power-handling capabilities and improved performance, and they are gaining popularity In conversion equipment. In this paper, the effects of internal parameters of GTO model using a circuit containing two transistors and three resistors the switching operation and the turn-off snubber characteristics is investigated using SPICE program.

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에미터 면적에 따른 BJT의 SPICE 1/f 잡음 파라미터 추출 (Extracting the BJT SPICE 1/f Noise Parameters Based on Emitter Area)

  • 홍현문;전병석;김주식
    • 조명전기설비학회논문지
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    • 제14권2호
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    • pp.43-45
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    • 2000
  • 본 연구에서는 BICMOS 공정으로 제조된 바이폴라 프렌지스터의 SPICE 잡음 파라미터 추출방법을 제시하였다. 기하학적 분석요로부터 $K_f$ 값이 에미터 면적에 반비례하고 있음을 보였다. 그리고 $K=0.8\times10_{-20}, A_f=2, \alpha=1$ 값이 추출되었다.

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4단자 GaAs MESFET Model의 SPICE 탑재 (Implementation of the Four-Terminal GaAs MESFET Model on SPICE)

  • 조남홍;곽계달
    • 전자공학회논문지A
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    • 제31A권1호
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    • pp.39-47
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    • 1994
  • The drain current reduction effect due to the side-gating phenomena resulted from interaction between the neighbor gates is lead to degradation of circuit performance. In this paper, these effect were modelized for circuit simulation with the shift of threshold voltage resulting from negative charge formation and the analysis of substrate leakage current resulting trapping effect. To remove dificiencies of the conventional three terminal structure, these model were implemented in SPICE with the four terminal structure, and then the constructed environment enables the simulation of circuit performance degradation resulted from side-gating effect. The validity of implemented model is proved by comparisoin with experiment data.

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3차원 SPICE 회로모델을 이용한 LED 신뢰성 분석 (Analysis of LED reliability using SPICE-based 3-dimensional circuit model)

  • 김진환;유순재;서종욱
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2008년도 하계종합학술대회
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    • pp.391-392
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    • 2008
  • A SPICE-based 3-dimensional circuit model of Light-Emitting Diode(LED) was modified include the reverse breakdown properties. The new model is found to be accurate to study the failure mechanisms of LEDs under electrostatic discharge (ESD) and electronic overstress (EOS). It was found that the permanent damages under heavy reverse stress is mainly due to the high electric field strength in P-GaN layer.

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과도상태 시뮬레이션을 사용한 OLED 픽셀 회로의 신뢰성 분석 방안 연구 (Study on the Reliability of an OLED Pixel Circuit Using Transient Simulation)

  • 정태호
    • 반도체디스플레이기술학회지
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    • 제20권4호
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    • pp.141-145
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    • 2021
  • The brightness of the Organic Light Emitting Diode (OLED) display is controlled by thin-film transistors (TFTs). Regardless of the materials and the structures of TFTs, an OLED suffers from the instable threshold voltage (Vth) of a TFT during operation. When designing an OLED pixel with circuit simulation tool such as SPICE, a designer needs to take Vth shift into account to improve the reliability of the circuit and various compensation methods have been proposed. In this paper, the effect of the compensation circuits from two typical OLED pixel circuits proposed in the literature are studied by the transient simulation with a SPICE tool in which the stretched-exponential time dependent Vth shift function is implemented. The simulation results show that the compensation circuits improve the reliability at the beginning of each frame, but Vth shifts from all TFTs in a pixel need to be considered to improve long-time reliability.