• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.15-22
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• 2011

Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.

• Journal of Powder Materials
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• v.17 no.2
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• pp.123-129
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• 2010

The fabrication of interconnect from titanium powders and $TiN_x$ powders is investigated. Corrosion-resistant titanium and $TiN_x$ are used as reinforcement in order to reveal high heat and corrosion resistance at the elevated temperature. We fabricated the plates for interconnect reinforced with $TiN_x$ by mixing titanium powders with 10 wt.% of nano-sized $TiN_x$. Spark Plasma Sintering (SPS) was chosen for the sintering of these composites. The plate made of titanium powders and $TiN_x$ powders demonstrates higher corrosion resistance than that of the plate of titanium powders alone. The physical properties of specimens were analyzed by performing hardness test and biaxial strength test. The electrochemical properties, such as corrosion resistance and hydrogen permeability at high temperature, were also investigated. The microstructures of the specimens were investigated by FESEM and profiles of chemical compositions were analyzed by EDX.

• Journal of the Microelectronics and Packaging Society
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• v.6 no.2
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• pp.37-43
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• 1999

Modules of the system that requires large capacity and high-speed information processing are implemented in the form of MCM that allows high-speed data processing, high density circuit integration and widely applied to such fields as ATM, GPS and PCS. Hence we developed the ATM switching module that is consisted of three chips and 2.48 Gbps data throughput, in the form of 10 multi-layer by Cu/Photo-BCB and 491pin PBGA which size is $48 \times 48 \textrm {mm}^2$. hnologies required for the development of the MCM includes extracting parameters for designing the substrate/package through the interconnect characterization to implement the high-speed characteristics, thermal management at the high-density MCM, and the generation of the testability that is one of the most difficult issues for developing the MCM. For the development of the ATM Switching MCM, we extracted signaling delay, via characteristics and crosstalk parameters through the interconnect characterization on the MCM-D. For the thermal management of 15.6 Watt under the high-density structure, we carried out the thermal analysis. formed 1.108 thermal vias through the substrate, and performed heat-proofing processing for the entire package so that it can keep the temperature less than $85^{\circ}C$. Lastly, in order to ensure the testability, we verified the substrate through fine pitch probing and applied the Boundary Scan Test (BST) for verifying the complex packaging/assembling processes, through which we developed an efficient and cost-effective product.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.1
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• pp.85-95
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• 2015

Network-on-chip (NoC) has evolved to overcome the issues of traditional bus-based on-chip interconnect. In NoC-reuse as TAM, the test schedulers are constrained with the topological position of cores and test access points, which may negatively affect the test time. This paper presents a scalable hybrid test data transportation scheme that allows to simultaneously test multiple heterogeneous cores of NoC-based SoCs, while reusing NoC as TAM. In the proposed test scheme, single test stimuli set of multiple CUTs is embedded into each flit of the test stimuli packets and those packets are multicast to the targeted CUTs. However, the test response packets of each CUT are unicast towards the tester. To reduce network load, a flit is filled with maximum possible test response sets before unicasting towards the tester. With the aid of Verilog and analytical simulations, the proposed scheme is proved effective and the results are compared with some recent techniques.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.79-90
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• 2005

In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST to improve the embedding probabilities of random-pattern-resistant-patterns. The proposed method uses a scan-cell reordering technique based on the signal probabilities of given test cubes and specific hardware blocks that increases the embedding probabilities of care bit clustered scan chain test cubes. We have developed a simulated annealing based algorithm that maximizes the embedding probabilities of scan chain test cubes to reorder scan cells, and an iterative algorithm for synthesizing the CRIN hardware. Experimental results demonstrate that the proposed CRIN BIST technique achieves complete fault coverage with lower storage requirement and shorter testing time in comparison with the conventional methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.105-116
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• 2008

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, we propose an efficient test access mechanism that exploits an on/off-chip bus bridge for the Advanced High-performance Bus (AHB) and Peripheral Component Interconnect (PCI) bus. The test application time is considerably reduced by providing dedicated test stimuli input paths and response output paths, and by excluding the bus direction tumaround delays. Experimental results show that area overhead and testing times are considerably reduced in both functional and structural test modes. The proposed technique can be a lied to the other types of on/off-chip bus bridges.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.68 no.2
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• pp.364-369
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• 2019

Generally, since memory chips should be tested all, considering its volume, the reduction in test time for detecting faults plays an important role in reducing the overall production cost. The parallel testing of chips in one ATE is a competitive solution to solve it. In this paper, NOC is proposed as test interface architecture between DUTs and ATE. Because NOC can be extended freely, there is no limit on the number of DUTs tested at the same time. Thus, more memory can be tested with the same bandwidth of ATE. Furthermore, the proposed NOC-based parallel test method can increase the efficiency of channel usage by packet type data transmission.

• Transactions of the Korean hydrogen and new energy society
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• v.16 no.1
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• pp.58-65
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• 2005

The $LaCrO_3$-dispersed Cr alloys for metallic interconnect of solid oxide fuel cell were prepared as a function of $LaCrO_3$ content in the range of 5 to 25 vol.% and were sintered at 1500$^{\circ}C$ under an Ar atmosphere with 5 vol.% $H_2$. The sintering and oxidation behaviors of these alloys were examined. The alloys indicated a good sinterability above 95% relative density at a given sintering condition, and their sintering densities is independent on $LaCrO_3$ content. The $LaCrO_3$ particles of the sintered alloys were concentrated on interfaces of Cr particles, and the size of the Cr particles increased with decreasing $LaCrO_3$ content, which is caused by inhibited grain growth of Cr particle by $LaCrO_3$ particle. The oxidation test showed all $LaCrO_3$-dispersed Cr alloys have good oxidation resistance as compared with pure Cr, which is attributed to presence of $LaCrO_3$ at the interface at which the oxidation reaction occurs rapidly. The Cr alloys with about 15 vol.% $LaCrO_3$ are very resistant to oxidation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.19-27
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• 2002

Characteristics of interconnect lines considering underlayer geometries of a silicon substrate and crossing metal lines are experimentally analyzed through elaborately devised patterns. In this work, test patterns for transmission lines having several kinds of underlayer geometries were devised, and the signal characteristics and responses are measured by S-parameter and time domain reflection meter (TDR). The patterns were designed and fabricated with a deep-submicron CMOS DRAM technology having 1 Tungsten and 2 Aluminum metals. From the analysis of measured results on the patterns, it is founded that the effects of underlayter line structures on line parameters (especially line capacitance and resistance) and signal distortions occurred from them cannot be negligible. The results provide useful and insightful understanding in the skew balance of package leads and global signal lines such as high-speed clock and data lines.

• Journal of the Microelectronics and Packaging Society
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• v.27 no.1
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• pp.45-54
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• 2020

Recently, market demands of miniaturization, high interconnection density, and fine pitch of PCBs continuously keep increasing. Therefore, SLP (substrate like PCB) technology using a modified semi additive process (MSAP) has attracted great attention. In particular, SLP technology is essential for the development of high-capacity batteries and 5G technology for smartphones. In this study, the reliability of the microvia of hybrid SLP, which is made of conventional HDI (high density interconnect) and MSAP technologies, was investigated by experimental and numerical analysis. Through thermal cycling reliability test using IST (interconnect stress test) and finite element numerical analysis, the effects of various parameters such as prepreg properties, thickness, number of layers, microvia size, and misalignment on microvia reliability were investigated for optimal design of SLP. As thermal expansion coefficient (CTE) of prepreg decreased, the reliability of microvia increased. The thinner the prepreg thickness, the higher the reliability. Increasing the size of the microvia hole and the pad will alleviate stress and improve reliability. On the other hand, as the number of prepreg layers increased, the reliability of microvia decreased. Also, the larger the misalignment, the lower the reliability. In particular, among these parameters, CTE of prepreg material has the greatest impact on the microvia reliability. The results of numerical stress analysis were in good agreement with the experimental results. As the stress of the microvia decreased, the reliability of the microvia increased. These experimental and numerical results will provide a useful guideline for design and fabrication of SLP substrate.