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A Clustered Reconfigurable Interconnection Network BIST Based on Signal Probabilities of Deterministic Test Sets  

Song Dong-Sup (Department of Electrical and Electronic Engineering, Graduate School, Yonsei University)
Kang Sungho (Department of Electrical and Electronic Engineering, Graduate School, Yonsei University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.12, 2005 , pp. 79-90 More about this Journal
Abstract
In this paper, we propose a new clustered reconfigurable interconnect network (CRIN) BIST to improve the embedding probabilities of random-pattern-resistant-patterns. The proposed method uses a scan-cell reordering technique based on the signal probabilities of given test cubes and specific hardware blocks that increases the embedding probabilities of care bit clustered scan chain test cubes. We have developed a simulated annealing based algorithm that maximizes the embedding probabilities of scan chain test cubes to reorder scan cells, and an iterative algorithm for synthesizing the CRIN hardware. Experimental results demonstrate that the proposed CRIN BIST technique achieves complete fault coverage with lower storage requirement and shorter testing time in comparison with the conventional methods.
Keywords
Deterministic Logic BIST; embedded core testing;
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