Journal of the Microelectronics and Packaging Society (마이크로전자및패키징학회지)

The Korean Microelectronics and Packaging Society (한국마이크로전자및패키징학회)
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Experimental and Numerical Analysis of Microvia Reliability for SLP (Substrate Like PCB)

실험 및 수치해석을 이용한 SLP (Substrate Like PCB) 기술에서의 마이크로 비아 신뢰성 연구

  • Cho, Youngmin (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology) ;
  • Choa, Sung-Hoon (Graduate School of NID Fusion Technology, Seoul National University of Science and Technology)
  • 조영민 (서울과학기술대학교 나노IT디자인 융합기술대학원) ;
  • 좌성훈 (서울과학기술대학교 나노IT디자인 융합기술대학원)
  • Received : 2020.02.07
  • Accepted : 2020.03.05
  • Published : 2020.03.30
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Abstract

Recently, market demands of miniaturization, high interconnection density, and fine pitch of PCBs continuously keep increasing. Therefore, SLP (substrate like PCB) technology using a modified semi additive process (MSAP) has attracted great attention. In particular, SLP technology is essential for the development of high-capacity batteries and 5G technology for smartphones. In this study, the reliability of the microvia of hybrid SLP, which is made of conventional HDI (high density interconnect) and MSAP technologies, was investigated by experimental and numerical analysis. Through thermal cycling reliability test using IST (interconnect stress test) and finite element numerical analysis, the effects of various parameters such as prepreg properties, thickness, number of layers, microvia size, and misalignment on microvia reliability were investigated for optimal design of SLP. As thermal expansion coefficient (CTE) of prepreg decreased, the reliability of microvia increased. The thinner the prepreg thickness, the higher the reliability. Increasing the size of the microvia hole and the pad will alleviate stress and improve reliability. On the other hand, as the number of prepreg layers increased, the reliability of microvia decreased. Also, the larger the misalignment, the lower the reliability. In particular, among these parameters, CTE of prepreg material has the greatest impact on the microvia reliability. The results of numerical stress analysis were in good agreement with the experimental results. As the stress of the microvia decreased, the reliability of the microvia increased. These experimental and numerical results will provide a useful guideline for design and fabrication of SLP substrate.

최근 PCB의 소형화, 박형화 및 고밀도화가 크게 요구되면서 MSAP (Modified Semi Additive Process) 기술을 이용한 SLP (Substrate Like PCB) 기술이 큰 주목을 받고 있다. 특히 SLP 기술은 스마트폰의 고용량 배터리 개발과 5G 기술에 꼭 필요한 기술이다. 본 연구에서는 기존의 HDI 기술과 MSAP 기술을 혼합하여 제작한 하이브리드 방식의 SLP의 신뢰성을 실험과 수치해석을 이용하여 분석하였다. 특히 최적의 SLP 설계를 위하여 프리프레그(prepreg)의 물성, 두께, 층수, 마이크로비아(microvia)의 크기 및 misalignment가 마이크로비아의 신뢰성에 미치는 영향을 IST(Interconnect Stress Test) 시험을 이용한 열사이클링 신뢰성 실험과 유한요소 수치해석을 통하여 고찰하였다. SLP 소재인 프리프레그의 열팽창계수가 적을수록 마이크로비아의 신뢰성은 크게 증가하며, 프리프레그의 두께가 얇을수록 신뢰성이 증가된다. 마이크로비아 홀의 크기 및 패드의 크기가 증가하면 응력이 완화되어 신뢰성은 향상된다. 반면 프리프레그의 층수가 증가할수록 마이크로비아의 신뢰성은 감소된다. 또한 misalignment가 크면 신뢰성은 감소하였다. 특히 이들 인자들 중에서 프리프레그의 열팽창계수가 마이크로비아의 신뢰성에 가장 큰 영향을 미친다. 수치 응력해석 결과도 실험 결과와 잘 일치하였으며, 응력이 낮을수록 마이크로비아의 신뢰성은 증가하였다. 본 실험과 수치해석의 결과는 향후 SLP 기판 제작 및 신뢰성 향상을 위한 유용한 설계 가이드라인으로 활용될 것으로 판단된다.

Keywords

References

  1. S. Cho, J. Jang, J. C. Kim, S. W. Kang, I. Seong, and K. Y. Bae, "A study on heat transfer characteristics of PCBs with a carbon CCL", J. Microelectron. Packag. Soc., 22(4), 37 (2015). https://doi.org/10.6117/kmeps.2015.22.4.037
  2. S. H. Huh, A. S. Shin, and S. J. Ham, "Ion migration failure mechanism for organic PCB under biased HAST", J. Microelectron. Packag. Soc., 22(1), 43 (2015). https://doi.org/10.6117/kmeps.2015.22.1.043
  3. F. Liu, J. Lu, V. Sundaram, D. Sutter, G. White, D. F. Baldwin, and R. R. Tummala, "Reliability assessment of microvias in HDI printed circuit boards", IEEE T. Compon. Pack. T., 25(2), 254 (2002). https://doi.org/10.1109/TCAPT.2002.1010014
  4. A. Renbi and J. Delsing, "A novel production process for $10\;{\mu}m$ microvias. In International Symposium on Microelectronics", International Microelectronics Assembly and Packaging Society, 2017(1), 000468 (2017).
  5. Y. Kitahara and J. Kang, "Ultra-fine patterning technology by utilizing nano-silver catalysts in MSAP" In 2018 International Conference on Electronics Packaging and iMAPS All Asia Conference (ICEP-IAAC), 112 (2018).
  6. M. Ibrahim, "The rising adoption of advanced substrates: IC substrate, SLP and embedded die, Chip Scale Review", 18 (2019).
  7. L. N. Ji, Y. Gong, and Z. G. Yang, "Failure investigation on copper-plated blind vias in PCB", Microelectron. Reliab., 50(8), 1163 (2010). https://doi.org/10.1016/j.microrel.2010.04.006
  8. A. Salahouelhadj, M. Martiny, S. Mercier, L. Bodin, D. Manteigas, and B. Stephan, "Reliability of thermally stressed rigid-flex printed circuit boards for High Density Interconnect applications", Microelectron. Reliab., 54(1), 204 (2014). https://doi.org/10.1016/j.microrel.2013.08.005
  9. Y. Ning, M. H. Azarian, and M. Pecht, "Effects of voiding on thermomechanical reliability of copper-filled microvias: Modeling and simulation", IEEE T. Device. Mat. Re., 15(4), 500 (2015). https://doi.org/10.1109/TDMR.2015.2476823
  10. D. H. Kim, S. J. Joo, D. O. Kwak, and H. S. Kim, "Warpage simulation of a multilayer printed circuit board and microelectronic package using the anisotropic viscoelastic shell modeling technique that considers the initial warpage", IEEE T. Comp. Pack. Man., 6(11), 1667 (2016).
  11. J. H. Lau, S. H. Pan, and C. Chang, "Creep analysis of solder bumped direct chip attach (DCA) on microvia build-up printed circuit board with underfill", In International Symposium on Electronic Materials and Packaging (EMAP), 127 (2000).
  12. L. N. Ji, Z. G. Yang, and J. S. Liu, "Failure analysis on blind vias of PCB for novel mobile phones", J. Fail. Anal. Prev., 8(6), 524 (2008). https://doi.org/10.1007/s11668-008-9174-1
  13. Y. Yang, "Reliabilities and failure analysis of printed circuit boards interconnect stress test", In 2018 19th International Conference on Electronic Packaging Technology (ICEPT), 428 (2018).
  14. K. Dusek, D. Busek, P. Hrzina, and J. Sevcik, "Thermal cycle testing of printed circuit board vias (Barrel Plates)", Proc. 41st International Spring Seminar on Electronics Technology (ISSE), 1 (2018).
  15. R. V. Pucha, G. Ramakrishna, S. Mahalingam, and S. K. Sitaraman, "Modeling spatial strain gradient effects in thermomechanical fatigue of copper microstructures", Int. J. Fatigue., 26(9), 947 (2004). https://doi.org/10.1016/j.ijfatigue.2004.01.008