Hybrid Test Data Transportation Scheme for Advanced NoC-Based SoCs |
Ansari, M. Adil
(Hanyang University)
Kim, Dooyoung (Hanyang University) Jung, Jihun (Hanyang University) Park, Sungju (Hanyang University) |
1 | M. A. Ansari, J. Song, M. Kim and S. Park, "Parallel test method for NoC-based SoCs," in Proc. IEEE International SoC Design Conference (ISOCC), 2009. |
2 | M. Agrawal, M. Richter and K. Chakrabarty, "A dynamic programming solution for optimizing test delivery in multicore SOCs," in Proc. IEEE International Test Conference (ITC), 2012. |
3 | T. SBIAI and K. NAMBA, "NoC Dynamically Reconfigurable as TAM," in Proc. IEEE 21st Asian Test Symposium (ATS), 2012. |
4 | J.-Y. Kim, J. Park, S. Lee, M. Kim, J. Oh and H.-J. Yoo, "A 118.4 GBps Multi-Casting Network-on-Chip with Hierarchical star-ring Combined Topology for Real-Time Object Recognition," IEEE Journal of Solid-State Circuits, vol. 45, no. 7, pp. 1399-1409, 2010. DOI ScienceOn |
5 | T. BJERREGAARD and S. MAHADEVAN, "A Survey of Research and Practices of Network-on-Chip," ACM Computing Surveys, vol. 38, no. 1, pp. 1-51, 2006. DOI ScienceOn |
6 | F. A. Samman, T. Hollstein and M. Glesner, "New Theory for Deadlock-Free Multicast Routing in Wormhole-Switched Virtual-Channelless Networkson-Chip," IEEE Transaction of Parallel and Distributed Systems, vol. 22, no. 4, pp. 544-557, 2011. DOI ScienceOn |
7 | S. Rodrigo, J. Flich, J. Duato and M. Hummel, "Efficient Unicast and Multicast Support for CMPs," in 41st IEEE/ACM International Symposium on Microarchitecture, MICRO-41. 2008, 2008. |
8 | S. Yan and B. Lin, "Custom Networks-on-Chip Architectures With Multicast Routing," IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 17, no. 3, pp. 342-355, 2009. DOI ScienceOn |
9 | R. Stefan, A. Molnos, A. Ambrose and K. Goossens, "A TDM NoC Supporting QoS, Multicast and Fast Connection Set-Up," in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012. |
10 | F. A. Samman, T. Hollstein and M. Glesner, "Planar Adaptive Network-on-Chip Supporting Deadlock-Free and Efficient Tree-Based Multicast Routing Method," Microprocessors and Microsystems, vol. 36, no. 6, pp. 449-461, 2012. DOI |
11 | N. John Mark and R. Mahapatra, "A TDM Test Scheduling Method for Network-on-Chip Systems," in Sixth IEEE International Workshop on Microprocessor Test and Verification MTV '05, 2005. |
12 | B. Fu, Y. Han, H. Li and X. Fi, "T2-TAM: Infrastructure Resource to Provide Parallel Testing for NoC based Chip," in Proc. 8th IEEE International Conference on ASIC, ASICON '09, 2009. |
13 | C. Liu, V. Iyengar, J. Shi and E. Cota, "Power-Aware Test Scheduling in Network-on-Chip Using Variable-Rate On-Chip Clocking," in Proc. 23rd IEEE VLSI Test Symposium, 2005. |
14 | J. H. Ahn and S. Kang, "Test Scheduling of NoCBased SoCs Using Multiple Test Clocks," ETRI Journal, vol. 28, pp. 475-485, 2006. DOI ScienceOn |
15 | J. H. Ahn and S. Kang, "NoC-Based SoC Test Scheduling Using Ant Colony Optimization," ETRI Journal, vol. 30, pp. 129-140, 2008. DOI ScienceOn |
16 | D. Xiang and Y. Zhang, "Cost-Effective Power-Aware Core Testing in NoCs Based on a New Unicast-Based Multicast Scheme," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, no. 1, pp. 135-147, 2011. DOI ScienceOn |
17 | M. Richter and K. Chakrabarty, "Optimization of Test Pin-Count, Test Scheduling, and Test Access for NoC-based Multicore SoCs," IEEE TRANSACTIONS ON COMPUTERS, SPECIAL ISSUE ON NETWORKS-ON-CHIP, [in press]. |
18 | E. Cota, M. Kreutz, C. A. Zeferino, L. Carro, M. Lubaszewski and A. Susin, "The Impact of NoC Reuse on the Testing of Core-based Systems," in Proc. IEEE 21st VLSI Test Symposium, 2003. |
19 | C. Liu, E. Cota, H. Sharif and D. K. Pradhan, "Test Scheduling for Network-on-Chip with BIST and Precedence Constraints," in Proc. IEEE International Test Conference, 2004. |
20 | S. K. Geol and E. J. Marinissen, "Effective and Efficient Test Architecture Design for SOCs," in Proc. IEEE International Test Conference, 2002. |
21 | T. Yoneda, M. Imanishi and H. Fujiwara, "An SoC Test Scheduling Algorithm using Reconfigurable Union Wrappers," in Proc. IEEE Design, Automation & Test in Europe Conference & Exhibition DATE '07, 2007. |
22 | V. Iyengar, K. Chakrabarty and E. J. Marinissen, "On Using Rectangle Packing for SoC Wrapper-TAM Co-Optimization," in Proc. IEEE 20th VLSI Test Symposium (VTS 2002), 2002. |
23 | S. Koranne and V. Iyengar, "On the Use of k - tuples for SoC Test Schedule Representation," in Proc. IEEE International Test Conference, 2002. |
24 | A. Larsson, E. Larsson, K. Chakrabarty, P. Eles and Z. Peng, "Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns," in Proc. IEEE Design, Automation and Test in Europe DATE '08, 2008. |
25 | V. Iyengar, K. Chankrabarty and E. J. Marinissen, "Test Wrapper and Test Access Mechanism Co- Optimization for System-on-Chip," 2001. |
26 | Y. Huang, W.-T. Cheng, C.-C. Tsai and N. Mukherjee, "Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC Design," in Proc. IEEE 10th Asian Test Symposium, 2001. |
27 | S. K. Goel and E. J. Marinissen, "A Novel Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips," in Proc. IEEE The Seventh EuropeanTest Workshop, 2002. |
28 | V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Efficient Test Access Mechanism Ooptimization for System-on-Chip," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 5, pp. 635-643, 2003. DOI ScienceOn |
29 | V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip," IEEE Trans. on Computers, vol. 52, no. 12, pp. 1619-1632, 2003. DOI ScienceOn |
30 | S. K. Geol and E. J. Marinissen, "SOC test architecture design for efficient utilization of test bandwidth," ACM Trans. on Design Automation of Electronic Systems (TODAES), vol. 8, no. 4, pp. 399-429, 2003. DOI ScienceOn |
31 | W. Zhang, L. Huo, L. Zuo, Z. Peng and W. Wu, "A Network on Chip Architecture and Performance Evaluation," in Proc. IEEE Second International Conference on Networks Security Wireless Communications and Trusted Computing (NSWCTC), 2010. |
32 | T. T. Ye, L. Benini and G. D. Micheli, "Packetization and routing analysis of on-chip multiprocessor networks," ELSEVIER Journal of Systems Architecture, vol. 50, no. 2-3, pp. 81-104, 2004. DOI ScienceOn |
33 | U. Y. Ogras and R. Marculescu, ""It's a small world after all": NoC performance optimization via long-range link insertion," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 7, pp. 693-706, 2006. DOI ScienceOn |
34 | J. H. Bahn, S. E. Lee and N. Bagherzadeh, "On Design and Analysis of a Feasible Network-on- Chip (NoC) Architecture," in Proc. IEEE Fourth International Conference on Information Technology ITNG '07, 2007. |
35 | M. A. Al Faruque, T. Ebi and J. Henkel, "AdNoC: Runtime Adaptive Network-on-Chip Architecture," IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 2, pp. 257-269, 2012. DOI ScienceOn |
36 | F. A. Samman, T. Hollstein and M. Glesner, "Multicast Parallel Pipeline Router Architecture for Network-on-Chip," in Proc. IEEE Design, Automation and Test in Europe DATE '08, 2008. |
37 | B. Attia, W. Chouchene, A. Zitouni, A. Nourdin and R. Tourki, "Design and implementation of low latency network interface for network on chip," in Proc. IEEE 5th International Design and Test Workshop (IDT), 2010. |
38 | K. Goossens and J. Dielissen, "A Ethereal Network on Chip: Concepts, Architectures and Implementations," IEEE Design & Test of Computers Journal, vol. 22, no. 5, pp. 414-421, 2005. DOI ScienceOn |
39 | S. Liu, A. Jantsch and Z. Lu, "Analysis and evaluation of circuit switched NoC and packet switched NoC," in 16th Euromicro Conference on Digital System Design, 2013. |
40 | E. J. Marinissen, V. Iyenger and K. Chakrabarty, "A set of benchmarks for modular testing of SOCs," in Proc. IEEE International Test Conference, 2002. |
41 | "AMBA AXI specifications," [Online]. Available:www.arm.com . |
42 | J. Duato, S. Yalamanchili and L. NI, Interconnect Networks: An Engineering Apprroach, San Francisco, USA: Morgan Kaufmann Publishers, 2003. |
43 | L. Benini and D. M. Giovanni, "Networks on Chips: A New SoC Paradigm," IEEE Computer Journal, vol. 35, no. 1, pp. 70-78, 2002. |
44 | X. Yang, Z. Qing-li, F. Fang-fa, Y. Ming-yan and L. Cheng, "NISAR: An AXI Compliant On-chip NI Architecture Offering Transaction Reordering Processing," in Proc. 7th IEEE International Conference on ASIC ASICON '07, 2007. |