• Title/Summary/Keyword: Information Processing Technology

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A Survivability Model of an Intrusion Tolerance System (침입감내시스템의 생존성 모델)

  • Park, Bum-Joo;Park, Kie-Jin;Kim, Sung-Soo
    • The KIPS Transactions:PartA
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    • v.12A no.5 s.95
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    • pp.395-404
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    • 2005
  • There have been large concerns about survivability defined as the capability of a system to perform a mission-critical role, in a timely manner, in the presence of attacks, failures. In particular, One of the most important core technologies required for the design of the ITS(Intrusion Tolerance System) that performs continuously minimal essential services even when the computer system is partially compromised because of intrusions is the survivability one of In included the dependability analysis of a reliability and availability etc. quantitative dependability analysis of the In. In this Paper, we applied self-healing mechanism utilizing two factors of self-healing mechanism (fault model and system response), the core technology of autonomic computing to secure the protection power of the ITS and consisted of a state transition diagram of the ITS composed of a primary server and a backup server. We also defined the survivability, availability, and downtime cost of the ITS, and then performed studies on simulation experiments and two cases of vulnerability attack. Simulation results show that intrusion tolerance capability at the initial state is more important than coping capability at the attack state in terms of the dependability enhancement.

Update Frequency Cache Consistency for Reducing Wait Time in Mobile Computing (이동 컴퓨팅 환경에서 대기 시간을 감소시키는 갱신 빈도 캐쉬 일관성 기법)

  • Lee, Chan-Seob;Kim, Dong-Hyuk;Baek, Joo-Hyun;Choi, Eui-In
    • The KIPS Transactions:PartD
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    • v.9D no.6
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    • pp.1017-1024
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    • 2002
  • According as mobile computing environment is generalized by development of wireless networking technology and communication device, mobile host uses local cache for extensibility and early response time. and reduction of limited bandwidth. This time, between mobile host and mobile support station cache need consistency interested person of done data accordingly much techniqueses propose. Existent consistency techniques because detection based techniqueses are used mainly and broadcast periodic invalid message considering frequent disconnection. However, these techniqueses increase abort step through increase or delay of transmission message number by accuracy examination of data. Therefore, because mobile host deletes cached data, and extensity are decreased. Techniques that is proposed in this paper did to perform refering update frequency about object that page request or when complete update operation happens to solve these problem. Therefore, have advantage that response is fast because could run write intention declaration or update by update frequency electively asynchronously when update operation consists and abort step decreases. Also, improved extensity running delete or propagation electively according to update frequency about periodic invalid message gone since disconnection.

Analysis of Performance, Energy-efficiency and Temperature for 3D Multi-core Processors according to Floorplan Methods (플로어플랜 기법에 따른 3차원 멀티코어 프로세서의 성능, 전력효율성, 온도 분석)

  • Choi, Hong-Jun;Son, Dong-Oh;Kim, Jong-Myon;Kim, Cheol-Hong
    • The KIPS Transactions:PartA
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    • v.17A no.6
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    • pp.265-274
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    • 2010
  • As the process technology scales down and integration densities continue to increase, interconnection has become one of the most important factors in performance of recent multi-core processors. Recently, to reduce the delay due to interconnection, 3D architecture has been adopted in designing multi-core processors. In 3D multi-core processors, multiple cores are stacked vertically and each core on different layers are connected by direct vertical TSVs(through-silicon vias). Compared to 2D multi-core architecture, 3D multi-core architecture reduces wire length significantly, leading to decreased interconnection delay and lower power consumption. Despite the benefits mentioned above, 3D design technique cannot be practical without proper solutions for hotspots due to high temperature. In this paper, we propose three floorplan schemes for reducing the peak temperature in 3D multi-core processors. According to our simulation results, the proposed floorplan schemes are expected to mitigate the thermal problems of 3D multi-core processors efficiently, resulting in improved reliability. Moreover, processor performance improves by reducing the performance degradation due to DTM techniques. Power consumption also can be reduced by decreased temperature and reduced execution time.

Vulnerability Analysis and Detection Mechanism against Denial of Sleep Attacks in Sensor Network based on IEEE 802.15.4 (IEEE 802.15.4기반 센서 네트워크에서 슬립거부 공격의 취약성 분석 및 탐지 메커니즘)

  • Kim, A-Reum;Kim, Mi-Hui;Chae, Ki-Joon
    • The KIPS Transactions:PartC
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    • v.17C no.1
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    • pp.1-14
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    • 2010
  • IEEE 802.15.4[1] has been standardized for the physical layer and MAC layer of LR-PANs(Low Rate-Wireless Personal Area Networks) as a technology for operations with low power on sensor networks. The standardization is applied to the variety of applications in the shortrange wireless communication with limited output and performance, for example wireless sensor or virtual wire, but it includes vulnerabilities for various attacks because of the lack of security researches. In this paper, we analyze the vulnerabilities against the denial of sleep attacks on the MAC layer of IEEE 802.15.4, and propose a detection mechanism against it. In results, we analyzed the possibilities of denial of sleep attacks by the modification of superframe, the modification of CW(Contention Window), the process of channel scan or PAN association, and so on. Moreover, we comprehended that some of these attacks can mount even though the standardized security services such as encryption or authentication are performed. In addition to, we model for denial of sleep attacks by Beacon/Association Request messages, and propose a detection mechanism against them. This detection mechanism utilizes the management table consisting of the interval and node ID of request messages, and signal strength. In simulation results, we can show the effect of attacks, the detection possibility and performance superiorities of proposed mechanism.

Accuracy of Parcel Boundary Demarcation in Agricultural Area Using UAV-Photogrammetry (무인 항공사진측량에 의한 농경지 필지 경계설정 정확도)

  • Sung, Sang Min;Lee, Jae One
    • Journal of the Korean Society of Surveying, Geodesy, Photogrammetry and Cartography
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    • v.34 no.1
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    • pp.53-62
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    • 2016
  • In recent years, UAV Photogrammetry based on an ultra-light UAS(Unmanned Aerial System) installed with a low-cost compact navigation device and a camera has attracted great attention through fast and accurate acquirement of geo-spatial data. In particular, UAV Photogrammetry do gradually replace the traditional aerial photogrammetry because it is able to produce DEMs(Digital Elevation Models) and Orthophotos rapidly owing to large amounts of high resolution image collection by a low-cost camera and image processing software combined with computer vision technique. With these advantages, UAV-Photogrammetry has therefore been applying to a large scale mapping and cadastral surveying that require accurate position information. This paper presents experimental results of an accuracy performance test with images of 4cm GSD from a fixed wing UAS to demarcate parcel boundaries in agricultural area. Consequently, the accuracy of boundary point extracted from UAS orthoimage has shown less than 8cm compared with that of terrestrial cadastral surveying. This means that UAV images satisfy the tolerance limit of distance error in cadastral surveying for the scale of 1: 500. And also, the area deviation is negligible small, about 0.2%(3.3m2), against true area of 1,969m2 by cadastral surveying. UAV-Photogrammetry is therefore as a promising technology to demarcate parcel boundaries.

Negative Transition of Smart Device Utility: Empirical Study on IT-enabled Work Flexibility, After Hours Work Connectivity, and Work-Life Conflict (스마트기기 효용의 부정적 전이: IT기반 업무 유연성, 근무시간 외 업무 연결성, 일-삶 갈등에 관한 실증 연구)

  • Kim, Hyung-Jin;Lee, Yoon-ji;Lee, Ho-Geun
    • Informatization Policy
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    • v.26 no.4
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    • pp.36-61
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    • 2019
  • While smart devices can have a positive impact on work efficiency and productivity by reducing time-space constraints and enabling rapid processing of tasks, side effects can arise from the imbalances between work and personal life. In recent years, as smart devices are increasingly used in work environments, it is more necessary than ever to understand the related phenomenon, find the cause of negative effects, and search for appropriate solutions. This study has developed and verified a theoretical model that shows how the technical characteristics known as the utility of smart devices are converted into negative results such as work-life conflict. As a result of analyzing the collected data from the employees, our study provides significant implications for the researchers, as well as the practitioners and policy makers, regarding various relationships among IT-enabled work flexibility, after-hours work connectivity and work-life conflict, and the new knowledge about the important role of segmentation supplies from the organization.

Implementation of Multiple-Valued Adder and Multiplier Using Current-Mode CMOS (전류모드 CMOS에 의한 다치 가산기 및 승산기의 구현)

  • Seong, Hyeon-Kyeong
    • The KIPS Transactions:PartA
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    • v.11A no.2
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    • pp.115-122
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    • 2004
  • In this paper, the multiple-valued adders and multipliers are implemented by current-mode CMOS. First, we implement the 3-valued T-gate and the 4-valued T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second we implement the circuits to be realized 2-variable 3-valued addition table and multiplication table over finite fields $GF(3^2)$, and 2-variable 4-valued addition table and multiplication table over finite fields $GF(4^2)$ with the multiple-valued T-gates. Finally, these operation circuits are simulated under $1.5\mutextrm{m}$ CMOS standard technology, $15\mutextrm{A}$ unit current, and 3.3V VDD voltage Spice. The simulation results have shown the satisfying current characteristics. The 3-valued adder and multiplier, and the 4-valued adder and multiplier implemented by current-mode CMOS is simple and regular for wire routing and possesses the property of modularity with cell array. Also, since it is expansible for the addition and multiplication of two polynomials in the finite field with very large m, it is suitable for VLSI implementation.

Generating Rank-Comparison Decision Rules with Variable Number of Genes for Cancer Classification (순위 비교를 기반으로 하는 다양한 유전자 개수로 이루어진 암 분류 결정 규칙의 생성)

  • Yoon, Young-Mi;Bien, Sang-Jay;Park, Sang-Hyun
    • The KIPS Transactions:PartD
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    • v.15D no.6
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    • pp.767-776
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    • 2008
  • Microarray technology is extensively being used in experimental molecular biology field. Microarray experiments generate quantitative expression measurements for thousands of genes simultaneously, which is useful for the phenotype classification of many diseases. One of the two major problems in microarray data classification is that the number of genes exceeds the number of tissue samples. The other problem is that current methods generate classifiers that are accurate but difficult to interpret. Our paper addresses these two problems. We performed a direct integration of individual microarrays with same biological objectives by transforming an expression value into a rank value within a sample and generated rank-comparison decision rules with variable number of genes for cancer classification. Our classifier is an ensemble method which has k top scoring decision rules. Each rule contains a number of genes, a relationship among involved genes, and a class label. Current classifiers which are also ensemble methods consist of k top scoring decision rules. However these classifiers fix the number of genes in each rule as a pair or a triple. In this paper we generalized the number of genes involved in each rule. The number of genes in each rule is in the range of 2 to N respectively. Generalizing the number of genes increases the robustness and the reliability of the classifier for the class prediction of an independent sample. Also our classifier is readily interpretable, accurate with small number of genes, and shed a possibility of the use in a clinical setting.

A study on traffic signal control at signalized intersections in VANETs (VANETs 환경에서 단일 교차로의 교통신호 제어방법에 관한 연구)

  • Chang, Hyeong-Jun;Park, Gwi-Tae
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.10 no.6
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    • pp.108-117
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    • 2011
  • Seoul metropolitan government has been operating traffic signal control system with the name of COSMOS since 2001. COSMOS uses the degrees of saturation and congestion which are calculated by installing loop detectors. At present, inductive loop detector is generally used for detecting vehicles but it is inconvenient and costly for maintenance since it is buried on the road. In addition, the estimated queue length might be influenced in case of error occurred in measuring speed, because it only uses the speed of vehicles passing by the detector. A traffic signal control algorithm which enables smooth traffic flow at intersection is proposed. The proposed algorithm assigns vehicles to the group of each lane and calculates traffic volume and congestion degree using traffic information of each group using VANETs(Vehicular Ad-hoc Networks) inter-vehicle communication. It does not demand additional devices installation such as cameras, sensors or image processing units. In this paper, the algorithm we suggest is verified for AJWT(Average Junction Waiting Time) and TQL(Total Queue Length) under single intersection model based on GLD(Green Light District) Simulator. And the result is better than Random control method and Best first control method. In case real-time control method with VANETs is generalized, this research that suggests the technology of traffic control in signalized intersections using wireless communication will be highly useful.

A Study on the Relationships between Busan Port and the Regional Economy (부산시 지역경제와 항만의 경제적 연계성 분석과 그 시사점)

  • Jung, Bong Min
    • Journal of Korea Port Economic Association
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    • v.30 no.4
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    • pp.199-217
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    • 2014
  • There have been relatively lots of studies on the relationships beteen port and city. And, most of the recent studies on the subject shows that the relationship between the two parties is weakening. The contributions of a port to the city economy such as convenience of logistics service utilization, cost reduction, creation of job opportunities and value added production etc. are diminishing, whereas negative effects of port such as environmental effects, limitation of waterfront activities etc. have been increasing. On the other hand, port logistics service demand from city economy is decreasing. As for Busan city, the trend of major economic indicators and growth factor analysis results show that there is hardly any relationships between the development of transportation industry(including port logistics) and the regional economy. Especially, it is identified that most regional industry sectors excluding transportation industry failed to secure competitive advantage. Accordingly, it can be concluded that Busan city economy fails to take advantage of advanced transportation industry sector, which supports overall economic activities. On the other hand, it can be a problem for enhancement of port-city relationships that related and supporting industries of transportation industry such as information and communication industry, financial and insurance industry, and processing and assembling manufacture industry fail to secure competitive advantage in Busan city.