References
- R. Kalla, S. Balaram, and J. M. Tendler, “IBM Power5 cip: a dual-core multithreaded processor,” IEEE MICRO, Vol.24, Issue 2, pp.40-47, 2004. https://doi.org/10.1109/MM.2004.1289290
- P. Kongetira, K. Aingaran, and K. Olukotun, “Niagara: a 32-way multithreaded Sparc processor,” IEEE MICRO, Vol.25, Issue 2, pp.21-29, 2005. https://doi.org/10.1109/MM.2005.35
- M. B. Taylor, J. Psota, A. Saraf, N. Shnidman, V. Strumpen, M. Frank, S. Amarasinghe, A. Agarwal, W. Lee, J. Miller, D. Wentzlaff, I. Bratt, B. Greenwald, H. Hoffmann, P. Johnson, and J. Kim, “Evaluation of the Raw microprocessor: an exposed-wire-delay architecture for ILP and Stremas,” In Proceedings of 31st annual International Symposium on Computer Architecture, pp.2-13, 2004. https://doi.org/10.1109/ISCA.2004.1310759
- K. Sankaralingam, R. Nagarajan, H. Liu, C. Kim, J. Huh, D. Burger, S. W. Keckler, and C. Moore, “Exploiting ILP, TLP, and DLP with the polymorphous trips architecture,” IEEE MICRO, Vol.23, Issue 6, pp.46-51, 2003. https://doi.org/10.1109/MM.2003.1261386
- V. Agarwal, M. S. Hrishikesh, S. W. Keckler, and D. Burger, “Clock rate versus IPC: the end of the road for conventional microarchitectures,” In Proceedings of the 27th International Symposium on Computer Architecture, pp.248-259, 2000. https://doi.org/10.1109/ISCA.2000.154905
- A. W. Topol, D. C. L. Tulipe, L. Shi, D. J. Frank, K. Bernstein, S. E. Steen, A. Kumar, G. U. Singco, A. M. Young, K. W. Guarini, and M. Ieong, “Three-dimensional integrated circuits,” IBM Journal of Research and Development, Vol.50, No.4/5, pp.491-506, 2006. https://doi.org/10.1147/rd.504.0491
- B. Black, M. Annavaram, N. Brekelbaum, J. DeVale, L. Jiang, G. H. Loh, D. McCaule, P. Morrow, D. W. Nelson, D. Pantuso, P. Reed, J. Rupley, S. Shankar, J. Shen, and C. Webb, “Die Stacking (3D) Microarchitecture,” In Proceedings of 39th International Symposium on Microarchitecture, pp.469-479, 2006. https://doi.org/10.1109/MICRO.2006.18
- S. W. Yoon, D. W. Yang, J. H. Koo, M. Padmanathan, and F. Carson, “3D TSV processes and its assembly/Packaging technology,” In Proceedings of IEEE International Conference on 3D System Integration, pp.1-5, 2009. https://doi.org/10.1109/3DIC.2009.5306535
- J. W. Joyner, and J. D. Meindl, “Opportunities for reduced power dissipation using three-dimensional integration,” In Proceedings of the IEEE 2002 international Interconnect Technology Conference, pp.148-150, 2002. https://doi.org/10.1109/IITC.2002.1014915
- B. Black, D. W. Nelson, C. Webb, and N. Samra, “3D Processing Technology and its Impact on IA32 Microprocessors,” In Proceedings of IEEE International Conference on Computer Design, pp.316-318, 2004. https://doi.org/10.1109/ICCD.2004.1347939
-
K. W. Guarini, A. W. Topol, M. Ieong, R. Yu, L. Shi, M.
R. Newport, D. J. Frank, D. V. Singh, G. M. Cohen, S. V.
Nitta, D. C. Boyd, P. A. O'Neil, S. L. Tempest, H. B. Pogge,
S. Purushothaman, and W. E. Haensch, “Electrical integrity
of state-of-the-art 0.13
${\mu}m$ SOI CMOS devices and circuits transferred for three-dimensional (3D) integrated circuit (IC) fabrication,” In Proceedings of the International Electron Devices Meeting, pp.943-945, 2005. https://doi.org/10.1109/IEDM.2002.1175992 - D. Nelson, C. Webb, D. McCauley, K. Raol, J. R. II, J. DeVale, and B. Black, “A 3D Interconnect Methodology Applied to iA32-class Architectures for Performance Improvements through RC Mitigation,” In Proceedings of the 21st International VLSI Multilevel Interconnection Conference, pp.78-83, 2004.
- P. Reed, G. Yeung, and B. Black, “Design Aspects of a Microprocessor Data Cache using 3D Die Interconnect Technology,” In Proceedings of the International Conference on Integrated Circuit Design and Technology, pp.15-18, 2005. https://doi.org/10.1109/ICICDT.2005.1502578
- K. Puttaswamy, and G. H. Loh, “Thermal Analysis of a 3D Die Stacked High Performance Microprocessor,” In Proceedings of ACM Great Lakes Symposium on VLSI, pp.19-24, 2006.
- L. Yeh, and R. Chy, “Thermal Management of Microelectronic Equipment,” American Society of Mechanical Engineering, 2001.
- R. Mahajan, “Thermal Management of CPUs: A Perspective on Trends, Needs, and Opportunities,” Invited talk given at the 8th International Workshop on THERMal INvestigations of ICs and Systems, 2002.
- S. Das, A. Chandrakasan, and R. Reif, “Timing, energy, and thermal performance of three-dimensional integrated circuits,” In Proceedings of ACM Great Lakes Symposium on VLSI, pp.338-343, 2004.
- J. Donald and M. Martonosi, “Techniques for multicore thermal management: Classification and new exploration,” In Proceedings of 33rd International Symposium on Computer Architecture, pp.78-88, 2006. https://doi.org/10.1109/ISCA.2006.39
- K. Skadron, M. R. Stan, W. Huang, S. Velusamy, K. Sankaranarayanan, and D. Tarjan, “Temperature-aware microarchitecture,” In Proceedings of 30th International Symposium on Computer Architecture, pp.2-13, 2003. https://doi.org/10.1109/ISCA.2003.1206984
- D. Brooks, and M. Martonosi, “Dynamic Thermal Management for High-Performance Microprocessors,” In Proceedings of High-Performance Computer Architecture, pp.171-182, 2001. https://doi.org/10.1109/HPCA.2001.903261
- J. Srinivasan, and S. V. Adve, “Predictive Dynamic Thermal Management for Multimedia Applications,” In Proceedings of International Continence Society, pp.109-120, 2003.
- S. Heo, K. Barr, and K. Asanovic, “Reducing Power Density through Activity Migration,” In Proceedings of international Symposium on Low Power Electronics and Design, pp.217-222, 2003. https://doi.org/10.1109/LPE.2003.1231865
- S. Chung and K. Skadron, “Using On-Chip Event Counters For High-Resolution, Real-Time Temperature Measurement,” In Proceedings of Thermal and Thermomechanical Phenomena in Electronics Systems, pp.114-120, 2006. https://doi.org/10.1109/ITHERM.2006.1645330
- K. Sankaranarayanan, S. Velusamy, M. Stan and K. Skadron, “A Case for Thermal-Aware Flooplanning at the Microacrchitecture Level,” Journal of Instruction-Level Parallelism, Vol.7, pp.1-16, 2005.
- SIA, “Technology Roadmap for Semiconductors,” 2005.
- P. Lindner, V. Dragoi, T. Glinsner, C. Schaefer, and R. Islam, “3D interconnect through aligned wafer level bonding,” In Proceedings of the Electronic Components and Technology Conference, pp.1439-1443, 2002. https://doi.org/10.1109/ECTC.2002.1008295
- P. Morrow, M. J. Kobrinsky, S. Ramanathan, C. M. Partk, M. Harmes, V. Ramachandrarao, H. M. Park, G. Kloster, S. List, and S. Kim, “Wafer-level 3D interconnects via Cu bonding,” In Proceedings of the 2004 Advanced Metalization Conference, pp.125-130, 2004.
- S. Reda, G. Smith, and L. Smith, “Maximizing the functional yield of wafer-to-wafer 3-D integration,” IEEE Transactions on Very Large Scale Lntegration (VLSI) Systems, Vol.17, No.9, pp.1357-1362, 2009. https://doi.org/10.1109/TVLSI.2008.2003513
- P. Leduca, F. de Crecy, B. Charlet, T. Enot, M. Zussy, B. Jones, J.-C. Barbe, N. Kernevez, N. Sillon, S. Maitrejean and D. Louisa, “Challenges for 3D IC integration: bonding quality and thermal management,” In Proceedings of IEEE Lnternational Lnterconnect Technology Conference, pp.210-212, 2007. https://doi.org/10.1109/IITC.2007.382392
- S. W. Yoon, D. W. Yang, J. H. Koo, M. Padmanathan and F. Carson, “3D TSV processes and its assembly/Packaging technology,” In Proceedings of IEEE International Conference on 3D System Integration, pp.1-5, 2009. https://doi.org/10.1109/3DIC.2009.5306535
- J. Cong, G. J. Luo, J. Wei and Y. Zhang, “Thermal-Aware 3D IC Placement Via Transformation,” In Proceedings of ASP-DAC (2007), pp.780-785, 2007. https://doi.org/10.1109/ASPDAC.2007.358084
- J. H. Choi, J. H. Kong, E. Y. Chung and S. W. Chung, “A Dual Integer Register File Structure for Temperature-Aware Microprocessor,” Journal of KIISE: Computer System and Theory, Vol.35, No.12, pp.540-551, 2008.
- R. E. Kessler, “The Alpha 21364 microprocessor,” IEEE MICRO, Vol.19, Issue 2, pp.24-36, 1996. https://doi.org/10.1109/40.755465
- D. Burger, T. M. Austin and S. Bennett, “Evaluating future microprocessors: the SimpleScalar tool set,” Technical Report TR-1308, University of Wisconsin-Madison Computer Sciences Department, 1997.
- W. Huang, M. R. Stan, K. Skadron, K. Sankaranarayanan and S. Ghosh, “HotSpot: A Compact Thermal Modeling Method for CMOS VLSI Systems,” IEEE Transactions on VLSI Systems, 2006.
- J. L. Henning, “SPEC CPU2000: measuring cpu performance in the new millennium,” IEEE Computer, Vol.33, No.7, pp.28-35, 2000. https://doi.org/10.1109/2.869367
- D. Brooks, V. Tiwari and M. Martonosi, “Wattch: A Framework for Architectural-level Power Analysis and Optimizations,” In Proceedings of the 27th Annual International Symposium on Computer Architecture, pp.83-94, 2000. https://doi.org/10.1109/ISCA.2000.154890
- A. K. Coskun, A. B. Kahng, T. S. Rosing, “Temperatureand Cost-Aware Design of 3D Multiprocessor Architectures,” In Proceedings of 12th Euromicro Conference on Digital System Design and Architectures, Methods and Tools, pp.183-190, 2009. https://doi.org/10.1109/DSD.2009.233