• 제목/요약/키워드: High voltage gain

검색결과 468건 처리시간 0.024초

넓은 범위의 전류 출력을 갖는 고선형 전압-제어 전류원 회로 (High-linearity voltage-controlled current source circuits with wide range current output)

  • 차형우
    • 대한전자공학회논문지SD
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    • 제41권7호
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    • pp.89-96
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    • 2004
  • 넓은 범위의 전압-제어 발진기 및 자동 이득 조절기의 실현을 위한 고선형 전압-제어 전류원(VCCS) 회로를 제안하였다. 제안한 VCCS는 전압 입력을 위해 이미터 폴로워, 전류 출력을 위해 이미터가 결합된 두 개의 공통-베이스 증폭기, 그리고 넓은 범위의 전류 출력과 높은 선형성을 얻기 위해 두 증폭기를 결합한 전류 미러로 구성된다. VCCS의 회로는 별도의 바이어스회로가 없이 단지 5개의 트랜지스터와 1개의 저항기만 사용하였다. 시뮬레이션 결과 제안한 VCCS는 5V의 공급전압에서 1V에서 4.8V까지의 제어-전압에 대하여 최대 0A에서 300㎃까지의 전류를 출력할 수 있다. 0㎃에서 300㎃의 출력 전류의 최대 선형 오차는 1.4 %이였다.

High-Gain Double-Bulk Mixer in 65 nm CMOS with 830 ${\mu}W$ Power Consumption

  • Schweiger, Kurt;Zimmermann, Horst
    • ETRI Journal
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    • 제32권3호
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    • pp.457-459
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    • 2010
  • A low-power down-sampling mixer in a low-power digital 65 nm CMOS technology is presented. The mixer consumes only 830 ${\mu}W$ at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 ${\pm}$1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of -5.9 dBm is achieved.

청력 보정을 위한 고주파 증폭 회로 설계 (Design of High Frequency Boosting Circuits Compensating for Hearing Loss)

  • 이광;정영진
    • 전자공학회논문지
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    • 제54권3호
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    • pp.138-144
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    • 2017
  • 본 논문에서는 노인성 난청으로 인한 청력도 감쇄를 보상하는 고주파 증폭 회로를 제안한다. 노인성 난청은 고음역(고주파 대역)의 청력도가 저음역(저주파대역)에 비해 더 떨어지는 저주파 통과 필터의 특성을 보이므로, 보상회로는 임계주파수 이상의 대역에서는 주파수에 비례하여 신호를 증폭하고 임계주파수 이하에서는 증폭도를 일정하게 유지하는 구조이다. 제안된 고주파 회로는 미분기, 단위 이득 증폭기로 구성된다. 임계주파수는 볼륨 조절 레버 형태로 간단하게 제어가 가능한 구조로 노인들이 자신의 난청정도에 따라 쉽게 증폭도를 조절할 수 있다. 고주파 증폭회로의 임계주파수는 가청주파수 전 대역에서 연속적으로 조절 가능하고, 10 kHz 음역의 신호는 80dB 이상 증폭도를 가진다.

Experimental Evaluation of Frequency Characteristics of Gain-saturated EDFA for Suppression of Signal Fluctuation in Terrestrial Free-space Optical Communication Systems

  • Yoo Seok, Jeong;Chul Han, Kim
    • Current Optics and Photonics
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    • 제7권1호
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    • pp.28-32
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    • 2023
  • Frequency characteristics of gain-saturated erbium-doped fiber amplifier (EDFA) are experimentally evaluated to mitigate the optical signal fluctuation induced by atmospheric turbulence in terrestrial freespace optical communication systems. Here, an acousto-optic modulator (AOM) is used to emulate optical signal fluctuations induced by atmospheric turbulence. The waveform which is generated in proportion to the refractive-index structural parameters is used to drive the AOM at various periodic frequencies. Thus, the dependence of the signal fluctuation suppression on the frequency is evaluated. The experiment is conducted using a periodic frequency sweep of the AOM driving voltage waveform and signal input power variation of the amplifier. It is observed that a low periodic frequency and high input signal power effectively suppress the optical signal fluctuation. This study evaluates the experimental results from the high-pass filter and gain-saturation characteristics of the EDFA.

Single-Electron Logic Cells and SET/FET Hybrid Integrated Circuits

  • Kim, S.J.;Lee, C.K.;Lee, J.U.;Choi, S.J.;Hwang, J.H.;Lee, S.E.;Choi, J.B.;Park, K.S.;Lee, W.H.;Paik, I.B.;Kang, J.S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • 제6권1호
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    • pp.52-58
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    • 2006
  • Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.

전해조건이 고순도 알루미늄 박 콘덴서의 터널에칭과 정전용량에 미치는 영향 (The Influence of Electrolytic Condition on Tunnel Etching and Capacitance Gain of High purity Aluminium Foil on capacitor)

  • 이재운;이병우;김용현;이광학;김흥식
    • 한국표면공학회지
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    • 제30권1호
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    • pp.44-56
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    • 1997
  • Influence of electrochemical etching conditions on capacitance gain of aluminium electrolytic on capacitor foil has been investigated by etching cubic textured high purity aluminum foil in dilute hydrochloric acid. Uniformly distributed etch pit tunnels on aluminum surface have been obtained by pretreatment aluminium foil in 10% NaOH solution for 5 minutes followed by electrochemical etching. Electrostatic capacitance of etched aluminium foil anodized to high voltage increased with the increase of current density, total charge, temperature and concentration of electrolyte up to maximum CV-value and then deceased. Election optical observation of the etched foil revealed that the density of etch of etch pits increased with the increase of current density and concentration of electrolyte. this increase of etch pit density enlarged of the increase of capacitance. However, abnormal high current density and high electrolyte concentration induced the local dissolution of the foil surface which resulted the decrease of foil capacitance.

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An Interleaved Five-level Boost Converter with Voltage-Balance Control

  • Chen, Jianfei;Hou, Shiying;Deng, Fujin;Chen, Zhe;Li, Jian
    • Journal of Power Electronics
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    • 제16권5호
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    • pp.1735-1742
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    • 2016
  • This paper proposes an interleaved five-level boost converter based on a switched-capacitor network. The operating principle of the converter under the CCM mode is analyzed. A high voltage gain, low component stress, small input current ripple, and self-balancing function for the capacitor voltages in the switched-capacitor networks are achieved. In addition, a three-loop control strategy including an outer voltage loop, an inner current loop and a voltage-balance loop has been researched to achieve good performances and voltage-balance effect. An experimental study has been done to verify the correctness and feasibility of the proposed converter and control strategy.

고속, 고해상도 CMOS 샘플 앤 홀드 회로 (High Speed, High Resolution CMOS Sample and Hold Circuit)

  • 김원연;박공순;박상욱;윤광섭
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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    • pp.545-548
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    • 2004
  • The paper describes the design of high-speed, high-resolution Sample-and-Hold circuit which shows the conversion rate 80MHz and the power supply of 3.3v with 0.35um CMOS 2-poly 4-metal process for high-speed, high resolution Analog-to-Digital Converter. For improving Dynamic performance of Sample-and-Hold, Two Double bootstrap switch and high performance operational amplifier with gain booster, which are used. and For physical stability of Sample and Hold circuit, reduces excess voltage of gate in bootstrap switch. Simulation results using HSPICE shows the SFDR of 71dB, 75dB in conversion rate of 80MHz result for two inputs(0.5Vpp, 10MHz and 1Vpp, 10MHz) and the power dissipation of 48mW at single 3.3V supply voltage.

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효율 개선을 위한 직${\cdot}$병렬 공진컨버터 적용 비접촉 전원 (Series-parallel resonant converter using a contactless power supply for the efficiency improvement)

  • 공영수;이현관;김은수;조정구;김종무
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2004년도 추계학술대회 논문집
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    • pp.45-48
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    • 2004
  • To improve the efficiency characteristics in the resonant converter using the contact-less power supply with the large air-gap and the long primary winding, this paper suggests the three-level series-parallel resonant converter(SPRC). The voltage gain characteristics of the proposed converter have the unit gain in a resonance frequency point of the series and parallel, and input voltage and current in the primary of SPRC are always In phase for the all equivalent load resistance because of the parallel resonant tank of the high impedance. The results are verified on the simulation based on the theoretical analysis and the 4kW experimental prototype.

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서인천 복합화력 발전소의 PSS 파라메터 Tuning (Field test Results for PSS Parameter Tuning in Seo-Incheon Power Plant)

  • 신정훈;김태균
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1998년도 하계학술대회 논문집 C
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    • pp.1143-1146
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    • 1998
  • Static excitation systems with high gain and fast response times greatly aid transient stability. but at the same time tend to reduce small signal stability. The objective of the power system stabilizer(PSS) control is to provide a positive contribution to damping of the generator rotor angle swings, which are in a broad range of frequencies in the power system. Therefore, this paper shows the field test results for the GE's EX2000 PSS tuning on units at Seo-Incheon power plant. The test is to verify that the PSS response meets GE's design, criteria. The responses of generator terminal voltage, active power, field voltage and current were analyzed and PSS gain was tuned by 10 finally.

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