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Single-Electron Logic Cells and SET/FET Hybrid Integrated Circuits  

Kim, S.J. (Dept. of Physics & Institute for NanoScience & Technology, Chungbuk National University)
Lee, C.K. (Dept. of Physics & Institute for NanoScience & Technology, Chungbuk National University)
Lee, J.U. (Dept. of Physics & Institute for NanoScience & Technology, Chungbuk National University)
Choi, S.J. (Dept. of Physics & Institute for NanoScience & Technology, Chungbuk National University)
Hwang, J.H. (Dept. of Physics & Institute for NanoScience & Technology, Chungbuk National University)
Lee, S.E. (Dept. of Physics & Institute for NanoScience & Technology, Chungbuk National University)
Choi, J.B. (Dept. of Physics & Institute for NanoScience & Technology, Chungbuk National University)
Park, K.S. (DRAM Process Architecture Team, Memory Division, SAMSUNG Electronics Co.,Ltd.)
Lee, W.H. (FLASH Device Engineering team, HYNIX Semiconductor Inc.)
Paik, I.B. (Electronics and Telecommunications Research Institute)
Kang, J.S. (R&D Center, LG Philips LCD Inc.)
Publication Information
Abstract
Single-electron transistor (SET)-based logic cells and SET/FET hybrid integrated circuits have been fabricated on SOI chips. The input-output voltage transfer characteristic of the SET-based complementary logic cell shows an inverting behavior where the output voltage gain is estimated to be about 1.2 at 4.2K. The SET/FET output driver, consisting of one SET and three FETs, yields a high voltage gain of 13 and power amplification with a wide-range output window for driving next circuit. Finally, the SET/FET literal gate for a multi-valued logic cell, comprising of an SET, an FET and a constant-current load, displays a periodic voltage output of high/low level multiple switching with a swing as high as 200mV. The multiple switching functionality of all the fabricated logic circuits could be enhanced by utilizing a side gate incorporated to each SET component to enable the phase control of Coulomb oscillations, which is one of the unique characteristics of the SET-based logic circuits.
Keywords
Silicon single-electron transistor(SET); SET complementary logic cell; SET output driver; SET/FET hybrid integrated circuit; SET/FET literal gate; SET/FET multi-functional logic cell;
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1 J. W. Park, K. S. Park, B. T. Lee, C. H. Lee, S. D. Lee, Jung B. Choi, K-H. Yoo, J. Kim, S. C. Oh, S. I. Park, K. T. Kim and J. J. Kim, 'Enhancement of Coulomb blockade and tunability by multidot coupling in a silicon-on-insulator-based singleelectron transistor,' Appl. Phys. Lett. vol.75, pp. 566-568. Jul. 1999   DOI
2 B. T. Lee, J. W. Park, K. S. Park, C. H. Lee, S. W. Paik, S. D. Lee, Jung B. Choi, K. S. Min, J. S. Park, S. Y. Hahn, T. J. Park, H. Shin, S. C. Hong, Kwyro Lee, H. C. Kwon, S. I. Park, K. T. Kim and K-H Yoo, 'Fabrication of a dual-gate-controlled Coulomb blockade transistor based on a silicon-on-insulator structure,' Semicond. Sci. Technol. Vol.13, pp. 1463-1467, Aug. 1998   DOI   ScienceOn
3 Y. Ono and Y. Takahashi, K. Yamazaki, M. Nagase, H. Namatsu, K. Kurihara and K. Murase, 'Fabrication method for IC-oriented Si singleelectron transistors,' IEEE Trans. Electron Devices, vol.47, pp.147-153, Jan. 2000   DOI   ScienceOn
4 S. Horiguchi, M. Nagase, K. Shiraishi, H. Kageshima, Y. Takahashi and K. Murase, 'Mechanism of Potential Profile Formation in Silicon Single-Electron Transistors Fabricated Using Pattern-Dependent Oxidation,' Jpn. J. Appl. Phys. vol.40, pp.L29-L32. Jan. 2001   DOI   ScienceOn
5 K.S. Park, S.J. Kim, I.B. Paik, W.H. Lee, J.S. Kang, Y.B. Jo, S.D. Lee, C.K. Lee, J.H. Kim, and J.B. Choi, THz ultra-fast single-electron transistors fabricated on SOI structures by PADOX,' Semicond. Sci. Technol., vol.19, L39-41, 2004   DOI   ScienceOn
6 K. Uchida, J. Koga, R. Ohba and A. Toriumi, 'Room-temperature operation of multifunctional single-electron transistor logic,' IEDM, 2001, pp.863-865   DOI
7 H. Mizuta, H. Muller, K. Tsukagoshi, D. Williams, Z. Durrant, A. Irvine, G. Evans, S. Amakawa, K. Nakazato and H. Ahmed, 'Nanoscale Coulomb blockade memory and logic devices,' Nanotechnol. vol.12, pp.155-159, June 2001   DOI   ScienceOn
8 H. Inokawa, A. Fujiwara and Y. Takahashi, 'A multiple-valued logic with merged single-electron and MOS transistors,' IEDM, 2001, pp.7.2.1-7.2.4   DOI
9 K.S. Park, S.J. Kim, I.B. Paik, W.H. Lee, J.S. Kang, Y.B. Jo, S.D. Lee, C.K. Lee, J.B. Choi, J.H. Kim, K.H. Park, W.J. Cho, M.G. Jang, S.J. Lee, 'SOI single-electron transistor with low RC delay for logic cells and SET/FET ICs,' IEEE Trans. Nanotechnology, vol.4, no.2, pp. 242-248, Mar. 2005   DOI   ScienceOn
10 R. H. Chen, A. N. Korotkov and K. K. Likarev, 'Single-electron transistor logic,' Appl. Phys. Lett. vol.68, pp.1954-1956, Apr. 1996   DOI
11 Y. Takahashi, A. Fujiwara, K. Yamazaki, H. Namatsu, K. Kurihara and K. Murase, 'Multigate single-electron transistors and their application to an exclusive-OR gate,' Appl. Phys. Lett. vol.76, pp.637-639, Jan. 2000   DOI   ScienceOn
12 C. P. Heij, D. C. Dixon, P. Hadley and J. E. Mooij, 'Negative differential resistance due to single-electron switching,' Appl. Phys. Lett. vol.74, pp. 1042-1044, Feb. 1999   DOI   ScienceOn