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http://dx.doi.org/10.4218/etrij.10.0209.0504

High-Gain Double-Bulk Mixer in 65 nm CMOS with 830 ${\mu}W$ Power Consumption  

Schweiger, Kurt (Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology)
Zimmermann, Horst (Institute of Electrodynamics, Microwave and Circuit Engineering, Vienna University of Technology)
Publication Information
ETRI Journal / v.32, no.3, 2010 , pp. 457-459 More about this Journal
Abstract
A low-power down-sampling mixer in a low-power digital 65 nm CMOS technology is presented. The mixer consumes only 830 ${\mu}W$ at 1.2 V supply voltage by combining an NMOS and a PMOS mixer with cascade transistors at the output. The measured gain is (19 ${\pm}$1 dB) at frequencies between 100 MHz and 3 GHz. An IIP3 of -5.9 dBm is achieved.
Keywords
Down-sampling mixer; low power; nanometer CMOS; bulk mixer;
Citations & Related Records

Times Cited By Web Of Science : 1  (Related Records In Web of Science)
Times Cited By SCOPUS : 1
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